Help me fix a VHDL syntax error

mo.khairy.mo · May 2, 2010

hi all
when i write this VHDL code

Code:

if ((a = 0) | (b = 0)) then
					
       c    <= (others=>'0');

end if;

i found this error

Code:

Syntax error near "|"

could anyone help me to fix this error

thanks in advance

FvM · May 2, 2010

VHDL syntax error

"|" isn't a defined standard VHDL operator. Did you mean "OR"?

mo.khairy.mo · May 2, 2010

VHDL syntax error

yeah i mean if either a=0 or b=0 and i don't want to check the result of a or b

vipinlal · May 3, 2010

Re: VHDL syntax error

Write the code like this :

Code:

if ((a = 0) or (b = 0)) then 
                
       c    <= (others=>'0'); 

end if;

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