library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity clock is
PORT(CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SEGMENT : OUT STD_LOGIC_VECTOR(6 downto 0);
DSELECT : OUT STD_LOGIC_VECTOR(3 downto 0) := "0000";
LEDs : OUT STD_LOGIC_VECTOR(3 downto 0));
end clock;
architecture clock_arch of clock is
signal clockcounter, count : INTEGER := 0;
signal tick : STD_LOGIC := '0';
signal countcode : STD_LOGIC_VECTOR(3 downto 0);
component decoder7segment
PORT (CODE : IN STD_LOGIC_VECTOR(3 downto 0);
DRIVER : OUT STD_LOGIC_VECTOR(6 downto 0));
end component;
begin
countcode <= CONV_STD_LOGIC_VECTOR(count,4);
LEDs <= countcode;
U1: decoder7segment PORT MAP (countcode,SEGMENT);
DSELECT(0) <= '0';
DSELECT(1) <= '1';
DSELECT(2) <= '1';
DSELECT(3) <= '1';
process(CLK,RESET)
begin
if(RESET = '1') then
clockcounter <= 0;
tick <= '0';
elsif(CLK = '1' AND CLK'EVENT) then
clockcounter <= clockcounter + 1;
end if;
if(clockcounter = 50000000) then
clockcounter <= 0;
count <= count + 1;
end if;
end process;
end clock_arch;