[SOLVED] help me figure out this simple VHDL bug

[ltkenbo]

I am using a Xilinx FPGA on a digilent FPGA demo board. Using Xilinx's ISE software I have written the following code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity clock is
	PORT(CLK : IN STD_LOGIC;
		  RESET : IN STD_LOGIC;
		  SEGMENT : OUT STD_LOGIC_VECTOR(6 downto 0);
		  DSELECT : OUT STD_LOGIC_VECTOR(3 downto 0) := "0000";
		  LEDs : OUT STD_LOGIC_VECTOR(3 downto 0));

		  
end clock;

architecture clock_arch of clock is

signal clockcounter, count : INTEGER := 0;
signal tick : STD_LOGIC := '0';
signal countcode : STD_LOGIC_VECTOR(3 downto 0);


component decoder7segment
PORT (CODE : IN STD_LOGIC_VECTOR(3 downto 0);
	  DRIVER : OUT STD_LOGIC_VECTOR(6 downto 0));
	
end component;

begin
	
   countcode <= CONV_STD_LOGIC_VECTOR(count,4);
	LEDs <= countcode;
	U1: decoder7segment PORT MAP (countcode,SEGMENT);
	DSELECT(0) <= '0';
	DSELECT(1) <= '1';
	DSELECT(2) <= '1';
	DSELECT(3) <= '1';

	process(CLK,RESET)
	begin
	
		if(RESET = '1') then
			clockcounter <= 0;
			tick <= '0';
		elsif(CLK = '1' AND CLK'EVENT) then
			clockcounter <= clockcounter + 1;
		end if;
		
		if(clockcounter  = 50000000) then
			clockcounter <= 0;
			
			count <= count + 1;
		end if;
		
	end process;
	

end clock_arch;

Basically it is supposed to increment a counter every second which is converted to binary and output to a 7 segment display (currently only supports 1 digit). I know my separate entity for the 7 seven decoder works fine because I have tested it, however for some reason this design is not counting correct. It should count from 0 upward, but instead it does the following sequence:

0 3 6 9 12 15 2 5 8 11 14 1 4 7 10 13

and then it goes back to 0. So it is counting through the whole sequence just not in the right order. I have read the value of my "countcode" variable through both the 7 segment and the LEDs on the board and have verified it is counting like that.

Why is this? I'm confused, I can't seem to figure out the problem. I took a basic class on VHDL design at my university (using altera) so I'm just trying to play around with some of my own stuff at home. Anyone see something I'm missing?

 

[TrickyDicky]

you need to put the count signal inside the clock.

 

[ltkenbo]

you need to put the count signal inside the clock.

You mean the whole count if statement?

- - - Updated - - -

Cool that worked. Why is it that it has to be within that same statement? Is it because of how it sequentially evaluates each statement? Sorry I'm new to VHDL and I'm still getting used to the hardware description aspect of it and thinking of it like programming still even though it is different.