library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity divide4 is
port (
clk : in std_logic;
rstn : in std_logic;
clk_by_4 : out std_logic);
end divide4;
architecture behave of divide4 is
signal count : std_logic_vector(2 downto 0);
begin -- behave
clk_by_4 <= count(2);
process (clk, rstn)
begin -- process
if rstn = '0' then -- asynchronous reset (active low)
count <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
count <= count + '1';
end if;
end process;
end behave;