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# Help me design this circuit

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#### Mr.Doyle

##### Newbie level 5
Pleace, can any one help me to solve this problem....I'm with trouble....really I need your help.

(a) Design the circuit shown below such that IDQ1 = 1mA, IDQ2 = 2mA, VDSQ1 = 4V, and VSDQ2 = 5V. The transistor parameters in the circuit in Fig. are: Kn1 = 0.1mA/V2, Kp2 = 1.0mA/V2, VTN1 = +2V, VTD2 = -2V, and λ1 = λ2 = 0. The circuit parameters are: VDD = 10V, RS1=4kΩ and Rin = 200kΩ. Calculate the small-signal voltage gain Av = vo/vi. Determine the maximum symmetrical swing in the output voltage. Assume the input is sinusoidal with amplitude 10mV and frequency 100kHz and all capacitors are 1uF.
(b) If a load of 1kΩ is connected at vo, what would be the new gain. Redesign the amplifier such that its gain will be almost independent of the load value.

and this is the circuit :

Thanks

Hi

The parameters: Kn1 and VTN1.....are they correct?

If I try to calculate Vgs1 I get 6.47V, but this leads to a gate voltage of 10.47V but exeeds the supply voltage of 10V!!!

Regards

Yes, they are correct.....
Kn1 = 0.1mA/V²
VTN1 = +2V

Hi

I have tried, but with the information given I cannot find a reasonable solution. Is there an W and L given for the transistors?
Otherwise I most refer to my previous post.

Do you have the solution?

P.S
Take a look in Sedra & Smith.....exellent book

Regards

Thanks a lot for tryng....
but all informations are given ...and this book which I have

Sorry don't have a solution to your problem but I would suggest that construct the circuit in SPICE for starters and test different resistor values to find your way.

Hi

You are given a specified current of 1mA in the the first transistor and a source resistor of 4KΩ. You can first calculate the drain resistance simply by saying

V_drain=I*R_source+Vds.....where Vds is equal to 4V.

So the resitance is R_drain=(Vdd-V_drain)/I=( 10-8 )/1mA=2KΩ

Now if you use the equation for a FET in saturated region:

I=½*Kn*(Vgs-Vtn)². Vgs=Gate-Source voltage

The unknow is Vgs, you can solve it by calculator and it will give you two solutions, only one is correct.

With the chosen Vgs, you a use this to calculate the two resistors at the gate....but this is where I have a problem, as I cannot get a valid solution.

The same approach can be used on the second branch.
But as mentioned in the previous post, try to simulate....I would like to know the answer if you do.

Regards

With the chosen Vgs, you a use this to calculate the two resistors at the gate.

how can I calculate the two resistors at the gate?

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