hi again
i want to map a design in a CPLD and then check it's functionality.this CPLD mounted on a board and is a part of close loop with other.it seems functionality will be checked with ChipScope during circuit's normal operation.
could anyone tell me how it would be?
tnx
RAM is used to store captured data. You define condition which will be used as a trigger for internal data capturing in real-time. After that you can download this data from FPGA through JTAG to analyse in PC. CPLD has no memory (just limited number of FFs), so there is no place to store captured data.
Altera has In-system Sources and Probes Editor that allows on-line debugging also with CPLD, with limit acquisition capabilities, but unlike Chipscope/SignalTap also as a stimulus. May be Xilinx has something similar?
Try Scanseer. It's a boundary-scan software like ChipScope, but it works with any chips that supports boundary-scan, not only Xilinx FPGAs. So it should work fine with your CPLD.
Try Scanseer. It's a boundary-scan software like ChipScope, but it works with any chips that supports boundary-scan, not only Xilinx FPGAs. So it should work fine with your CPLD.