Help me design a divide-by-5 sequential circuit with 50% duty cycle.

[seemagoyal44]

Design a divide-by-5 sequential circuit with 50% duty cycle.

 

[shockie]

Re: divide by 5

Please search and you will find a paper about "clock divider made easy" in this forum. The idea, I think, is to double clock first and then divide it. you will get N=odd clock divider.[/img]

 

[donald007]

divide by 5

Is there another way to do this? Because our PLL may not provide 2f clock in current project.

2f: double frequency

 

[wangrunlai]

Re: divide by 5

Design a divide-by-5 sequential circuit with 50% duty cycle.

module DIV5(rst_i, clk_i, div_clk_o);
input rst_i;
input clk_i;
output div_clk_o;
reg div_clk_o;
reg [2:0] count;

always@(posedge clk_i or posedge rst_i)
if(rst_i)
count <= 3'd0;
else if(count == 3'b4)
count <= 3'd0;
else
count <= count + 1'b1;

always(posedge clk_i or posedge rst_i)
if(rst_i)
div_clk_o <= 1'b0;
else if(count == 3'd4)
div_clk_o <= ~div_clk_o;
else
div_clk_o <= div_clk_o;

always(negedge clk_i or posedge rst_i)
if(rst_i)
div_clk_o <= 1'b0;
else if(count == 3'd2)
div_clk_o <= ~div_clk_o;
else
div_clk_o <= div_clk_o;

endmodule