Oct 31, 2007 #1 S seemagoyal44 Member level 1 Joined Oct 20, 2007 Messages 39 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,535 Design a divide-by-5 sequential circuit with 50% duty cycle.
Oct 31, 2007 #2 S shockie Advanced Member level 4 Joined Jul 10, 2002 Messages 100 Helped 6 Reputation 12 Reaction score 4 Trophy points 1,298 Activity points 500 Re: divide by 5 Please search and you will find a paper about "clock divider made easy" in this forum. The idea, I think, is to double clock first and then divide it. you will get N=odd clock divider.[/img]
Re: divide by 5 Please search and you will find a paper about "clock divider made easy" in this forum. The idea, I think, is to double clock first and then divide it. you will get N=odd clock divider.[/img]
Nov 1, 2007 #3 D donald007 Newbie level 6 Joined Aug 28, 2007 Messages 11 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,281 Location TAIWAN Activity points 1,336 divide by 5 Is there another way to do this? Because our PLL may not provide 2f clock in current project. 2f: double frequency
divide by 5 Is there another way to do this? Because our PLL may not provide 2f clock in current project. 2f: double frequency
Nov 1, 2007 #4 W wangrunlai Junior Member level 2 Joined Mar 29, 2005 Messages 20 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,400 Re: divide by 5 seemagoyal44 said: Design a divide-by-5 sequential circuit with 50% duty cycle. Click to expand... module DIV5(rst_i, clk_i, div_clk_o); input rst_i; input clk_i; output div_clk_o; reg div_clk_o; reg [2:0] count; always@(posedge clk_i or posedge rst_i) if(rst_i) count <= 3'd0; else if(count == 3'b4) count <= 3'd0; else count <= count + 1'b1; always(posedge clk_i or posedge rst_i) if(rst_i) div_clk_o <= 1'b0; else if(count == 3'd4) div_clk_o <= ~div_clk_o; else div_clk_o <= div_clk_o; always(negedge clk_i or posedge rst_i) if(rst_i) div_clk_o <= 1'b0; else if(count == 3'd2) div_clk_o <= ~div_clk_o; else div_clk_o <= div_clk_o; endmodule
Re: divide by 5 seemagoyal44 said: Design a divide-by-5 sequential circuit with 50% duty cycle. Click to expand... module DIV5(rst_i, clk_i, div_clk_o); input rst_i; input clk_i; output div_clk_o; reg div_clk_o; reg [2:0] count; always@(posedge clk_i or posedge rst_i) if(rst_i) count <= 3'd0; else if(count == 3'b4) count <= 3'd0; else count <= count + 1'b1; always(posedge clk_i or posedge rst_i) if(rst_i) div_clk_o <= 1'b0; else if(count == 3'd4) div_clk_o <= ~div_clk_o; else div_clk_o <= div_clk_o; always(negedge clk_i or posedge rst_i) if(rst_i) div_clk_o <= 1'b0; else if(count == 3'd2) div_clk_o <= ~div_clk_o; else div_clk_o <= div_clk_o; endmodule