fet multiplier circuit
activewei said:
I would suggest you to design with Step recovery diode. The required input driving power is relative low and therefore the efficiency is higher. to get 20dBm of output power, it is necessary to add an amplifier after the multiplier (common practice)
The step recovery diode design is very suitable for high frequency design.But for camel_RF design requirement,a FET multipler is ok enough.tTune the output match circuit to 3rd harmonic and input match to fundmental.additional gain stage is required.AWR Microwave Office have a such example,its design note is below.
FET Multiplier
This project demonstrates how to set up MWO for the nonlinear simulation of a FET frequency doubler. Also, it demonstrates some of the new capability found in v6, such as using the tuner to control the display of pre-simulated data. The tuner is also employed in the same fashion that previous versions of MWO employed, namely to tune element parameters through defined states using equations and variables. The tuner is a very powerful tool allowing complex simulations to be brought under the control of the designer, and refined.
Overview
This multiplier uses a single transistor whose bias is fixed at just below the specified pinch off voltage of the channel; this ensures that the device produces an output waveform that has a fairly strong second harmonic content. Other arrangements are possible, such as combining two transistors in anti-phase, but for the purposes of this example project one transistor is used. With this simulation two parameters are being used to explore the circuit behavior, namely frequency and drive power. The drive frequency is defined using the individual options for each schematic. With MWO v6 all circuits (linear, nonlinear and EM) own their own frequency ranges. Right click on 'FET Frequency Multiplier' in the Circuit Schematics browser and select the options in the menu. Here, one will see the frequency list used to define the simulation frequency set. To define the drive level, an equation has been placed in the schematic that sets up the range of power values. A complimentary equation defines a variable (Power) that is indexed to the list of potential powers used in the simulation. In this example, the list of power levels is defined by the statement ‘PowerStates = stepped(9,13,0.5)’.
DC and Dynamic IV
The instantaneous voltage at the device terminals is plotted along with the DC static IV curves. These serve to give some insight into the device behavior under these extreme drive conditions. As a check on the bias conditions, edit the schematic 'FET Frequency Multiplier' and substitute the number -20 in place of the variable in the power parameter for the input port. Re-simulate and the quiescent operating point will be seen. The schematic 'FET DC IV Tests' is used for the simulation of the DC IV curves of the transistor.
Output Spectrum
To assist the designer in seeing the actual drive frequency and the frequency of the associated second harmonic, markers have been added to the traces of the fundamental and second harmonics. The markers will update whilst the tuner is being used giving instant feedback as to the drive frequency. To see the marker snap to the trace, after each movement of the tuner control release the mouse button before moving the tuner control to the next position.
Waveforms
The time domain plot of the multiplication process can readily be seen when comparing the drive waveform and the load waveform. Use the tuner to vary either the drive level or select the drive frequency simulation results.
Tuning
The dynamic IV measurement (IVDLL) makes use of the new tune feature of v6. This new feature allows the designer to select a pre-simulated trace using the tuner. In this project, the IVDLL is calculated for all the frequencies associated with the project, the tuner allows the display of a single trace.
The bitmap below illustrates how the measurement dialog is used to use the tuner to select a specific simulation result.