superhet said:and one thing more. i entered my code in Xilinx ISE but the synthesis report tells me that there is no clock signal in my design. do i have to use some specific keywords for the clock signal.
superhet said:Renjith can you give me sample code for the 16-bit counter?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity superhet_clkdivider is
Port ( clk : in std_logic;
rst : in std_logic;
clkout : out std_logic);
end superhet_clkdivider;
architecture Behavioral of superhet_clkdivider is
signal count : std_logic_vector(14 downto 0);
-- Terminal Count Hexadecimal value for 62500/2
constant TerminalCount : std_logic_vector:=x"7a12";
signal clk400 : std_logic;
begin
Process(clk,rst)
begin
if rst = '0' then
count <= (others=>'0');
clk400 <= '0';
elsif clk'event and clk = '1' then
if count < Terminalcount then
count <= count + 1;
else
count <= (others=>'0');
clk400 <= not clk400;
end if;
end if;
end process;
clkout <= not clk400;
end Behavioral;
Here's the verilog eq. of Renjith's code:superhet said:i dont want clk2 to be driven by an external clock. i want it to be driven from clk. for that i would need a clock divider and i need it in verilog.
ill be waiting for your reply
module superhet_clkdivider (clk, rst, clkout);
input clk;
input rst;
output clkout;
wire clkout;
reg[14:0] count;
parameter TerminalCount = 16'h7a12 ;
reg clk400;
always @(clk or rst)
begin
if (rst == 1'b0)
begin
count <= {15{1'b0}} ;
clk400 <= 1'b0 ;
end
else if (clk == 1'b1)
begin
if (count < TerminalCount)
begin
count <= count + 1 ;
end
else
begin
count <= {15{1'b0}} ;
clk400 <= ~clk400 ;
end
end
end
assign clkout = ~clk400 ;
endmodule
module top (clk, clkout);
parameter divider = 25000000 / 400; // must be an even number
input clk;
reg [15:0] count = 0;
output reg clkout = 0;
always @ (posedge clk) begin
count <= count == (divider / 2 - 1) ? 0 : count+1;
clkout <= clkout + (count == 0);
end
endmodule
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