Your schematics are incomplete as to say which one is better. Whenever flipflops comes into picture clock comes into account. Clock routing or simulations are most critical regarding matching parasitics in layout designing or balancing the skew for PNR blocks.
If the output of the inverters/buffers are going to the CLK pin of the flipflop then 1st schematic should be considered as it serves the purpose for both layout designing & PNR block. But if the output is going to any pin then 2nd schematic is better as it saves area for layout designing and for PNR block it reduces additional net delays & net routings.