I'm designing a CMOS inverter circuit.
Right side graph is output voltage.
My question is why is there a peaking at 1us, 2us, ...(yellow mark)
and how can i remove it?
It is caused by the gate-drain capacitance of the MOSFETs, which directly couple the input signal to the output. If you slow the rise time of the input signal, the spike should get smaller or disappear.