Hello, I hope you guys doing well.
This is one part of a school project, I did the other parts but I'm stuck on this one:
"This given module take the 50 MHz clock_50 of the DE2 board and divides down to generate a CLKout of 1 Hz. Modify this given module to make the clock twice as fast or 2 Hz"
The original code has a very common bug. "count" will go from 0 to 25000000 and then start from zero again. That is a 25000001 cycle interval, so the frequency divisor is 50000002, not 50000000.
Also, "count" as an integer without range will probably synthesize to 32 bits. I doubt that the synthesis tool is smart enough to reduce it to 25 bits, which is enough. Either put a range on "count", or define it as "unsigned" with the correct size.