#### saUNT

##### Newbie level 3

Hello, I hope you guys doing well.

This is one part of a school project, I did the other parts but I'm stuck on this one:

"This given module take the 50 MHz clock_50 of the DE2 board and divides down to generate a CLKout of 1 Hz. Modify this given module to make the clock twice as fast or 2 Hz"

and here is the code:

This is one part of a school project, I did the other parts but I'm stuck on this one:

"This given module take the 50 MHz clock_50 of the DE2 board and divides down to generate a CLKout of 1 Hz. Modify this given module to make the clock twice as fast or 2 Hz"

and here is the code:

Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DIVIDER is port ( CLKin: in std_logic; reset: in std_logic; CLKout: out std_logic); end DIVIDER; architecture behavioral of DIVIDER is signal count: integer:=0; signal temp : std_logic := '1'; begin process(CLKin,count,reset) begin if(reset='1') then count<=0; temp<='1'; elsif(CLKin'event and CLKin='1') then count <=count+1; if (count = 25000000) then temp <= NOT temp; count<=0; end if; end if; CLKout<= temp; end process; end behavioral;

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