[SOLVED] help:make the clock divider twice as fast or 2 Hz.

[saUNT]

Hello, I hope you guys doing well.
This is one part of a school project, I did the other parts but I'm stuck on this one:

"This given module take the 50 MHz clock_50 of the DE2 board and divides down to generate a CLKout of 1 Hz. Modify this given module to make the clock twice as fast or 2 Hz"

and here is the code:

---

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity DIVIDER is
port ( CLKin: in std_logic;
reset: in std_logic;
CLKout: out std_logic);
end DIVIDER;
 
architecture behavioral of DIVIDER is
signal count: integer:=0;
signal temp : std_logic := '1';
begin
process(CLKin,count,reset)
begin
if(reset='1') then count<=0; temp<='1';
elsif(CLKin'event and CLKin='1') then count <=count+1;
if (count = 25000000) then temp <= NOT temp; count<=0;
end if;
end if;
CLKout<= temp;
end process;
end behavioral;

---

 

[TrickyDicky]

What exactly is the problem (apart from the fact that clock dividers like this are bad practice)?

 

[saUNT]

The teacher is wanting to "Modify this given module to make the clock twice as fast or 2 Hz" but i really don't understand what he is asking

 

[fouwad]

if (count = 25000000) then temp <= NOT temp; count<=0;

just make the value half, problem solved

 

[std_match]

The original code has a very common bug. "count" will go from 0 to 25000000 and then start from zero again. That is a 25000001 cycle interval, so the frequency divisor is 50000002, not 50000000.

Also, "count" as an integer without range will probably synthesize to 32 bits. I doubt that the synthesis tool is smart enough to reduce it to 25 bits, which is enough. Either put a range on "count", or define it as "unsigned" with the correct size.