hello,
many EDA tools support low power design
anyone can tell me what kind of low power techniques supportted by the EDA vendor (cadence, synopsys, MAGMA...)?
i know the synthesis tools have switch active reduction, clock gating, operand isolation & multi-Vth optimization, and any else?
the APR tools can handle voltage island (level shift), and any else?
thanks
best regards
Another technology called clock mesh , but i don't know which APR tools support it. clock have a huge drive , and use clock mesh can reduce skew and power .
I went through a tool from Golden gate Technology.It seems it will compliment the existing flows for low power.It takes the design during P&R , does a push button low power optimization and give back to P&R tools for further processing.Company claims nearly 25 % power reduction!!