modelsim error 3043
Hi,
Thanks for all the reply.
echo47, the website you gave me is very helpful.
Anyways, I have encounter new problems. When I ran my simulation, Modelsim give me this error:
# ** Error: C:/Xilinx/verilog/src/simprims/X_FF.v(55): $recovery( negedge RST:21034 ps, posedge CLK &&& (rst_clk_enable == 1):21200 ps, 404 ps );
# Time: 21200 ps Iteration: 1 Instance: /tb_htg_map/UUT/\htg/tg_cgen_ise/clk2_out_356\
# ** Error: C:/Xilinx/verilog/src/simprims/X_FF.v(55): $recovery( negedge RST:8601621034 ps, posedge CLK &&& (rst_clk_enable == 1):8601621200 ps, 404 ps );
# Time: 8601621200 ps Iteration: 1 Instance: /tb_htg_map/UUT/\htg/tg_cgen_ise/clk2_out_356\
# ** Error: C:/Xilinx/verilog/src/simprims/X_FF.v(55): $recovery( negedge RST:8813621034 ps, posedge CLK &&& (rst_clk_enable == 1):8813621200 ps, 404 ps );
# Time: 8813621200 ps Iteration: 1 Instance: /tb_htg_map/UUT/\htg/tg_cgen_ise/clk2_out_356\
FYI, I already check in Xilinx website as u suggested. But no match.
How to fix recovery error for Xilinx FPGA design?
Thus, anyone of you faced this error before. Please share it, highly appreciated.
Thanx in advance,
-no_mad