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Help: ISE with ModelSim simulation issue

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no_mad

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vsim-3389

Hi all,

Currently, I’m using ISE v7.1i with ModelSim SE as the simulator.

Previously, I’ve synthesized my code with DC and verified it with NC-Verilog. No problem.

But now, I want to transfer my rtl into Spartan-II. In ISE project navigator, I ran a post-translate simulation. It showed this error in ModelSim SE 6.0D:

# ** Error: (vsim-3043) C:/Documents and Settings/Xtoon/My Documents/My Work/AFE/TA5/ISE_post/tb_htgtrans.v(32): Unresolved reference to 'glbl' in glbl.GTS.
# Region: /tb_htgtrans
# ** Error: (vsim-3043) C:/Documents and Settings/Xtoon/My Documents/My Work/AFE/TA5/ISE_post/htg_trans.v(2583): Unresolved reference to 'glbl' in glbl.GTS.
# Region: /tb_htgtrans/UUT
# Loading work.ffsrce
# ** Warning: (vsim-3620) C:/Documents and Settings/Xtoon/My Documents/My Work/AFE/TA5/ISE_post/htg_trans.v(129): Specify path destination port 'O' has no drivers on it.
# Region: /tb_htgtrans/UUT/sif_sifadr5_adr4_8
# ** Error: (vsim-3389) C:/Documents and Settings/Xtoon/My Documents/My Work/AFE/TA5/ISE_post/htg_trans.v(2629): Port '(null)' not found in the connected module (1st connection).
# Region: /tb_htgtrans/UUT/h_tg_htg_cpdm_tr_dec_1_13__xor
# ** Error: (vsim-3389) C:/Documents and Settings/Xtoon/My Documents/My Work/AFE/TA5/ISE_post/htg_trans.v(2629): Port '(null)' not found in the connected module (2nd connection).
# Region: /tb_htgtrans/UUT/h_tg_htg_cpdm_tr_dec_1_13__xor
# ** Error: (vsim-3389) C:/Documents and Settings/Xtoon/My Documents/My Work/AFE/TA5/ISE_post/htg_trans.v(2629): Port '(null)' not found in the connected module (3rd connection).
# Region: /tb_htgtrans/UUT/h_tg_htg_cpdm_tr_dec_1_13__xor
# ** Error: (vsim-3389) C:/Documents and Settings/Xtoon/My Documents/My Work/AFE/TA5/ISE_post/htg_trans.v(2629): Port '(null)' not found in the connected module (4th connection).
# Region: /tb_htgtrans/UUT/h_tg_htg_cpdm_tr_dec_1_13__xor
# ** Error: (vsim-3389) C:/Documents and Settings/Xtoon/My Documents/My Work/AFE/TA5/ISE_post/htg_trans.v(2629): Port '(null)' not found in the connected module (5th connection).
# Region: /tb_htgtrans/UUT/h_tg_htg_cpdm_tr_dec_1_13__xor
# ** Error: (vsim-3389) C:/Documents and Settings/Xtoon/My Documents/My Work/AFE/TA5/ISE_post/htg_trans.v(2629): Port '(null)' not found in the connected module (6th connection).
# Region: /tb_htgtrans/UUT/h_tg_htg_cpdm_tr_dec_1_13__xor
# ** Error: (vsim-3389) C:/Documents and Settings/Xtoon/My Documents/My Work/AFE/TA5/ISE_post/htg_trans.v(2629): Port '(null)' not found in the connected module (7th connection).
# Region: /tb_htgtrans/UUT/h_tg_htg_cpdm_tr_dec_1_13__xor
# ** Fatal: (vsim-3365) C:/Documents and Settings/Xtoon/My Documents/My Work/AFE/TA5/ISE_post/htg_trans.v(2629): Too many port connections. Expected 3, found 10.

# FATAL ERROR while loading design
# Error loading design


Please help me out here. Any comments and/or suggestions are welcome.

Thanx in advance,
-no_mad
 

Ahmed Ragab

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too many port connections modelsim

have you transeferred all the libraries in ISE to your modelsim SE ?!
notice that there are some differences between both of them

If you haven't done so already then you need to work in the comand window
and write down:
compxlib -help
it will help you all the way untill you transfer all libraries to modelsimSE
 

echo47

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too many port connections. modelsim

Also see "Compiling Xilinx Simulation Libraries (COMPXLIB)" in your Synthesis and Verification Design Guide.

More related info:
https://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=15338

There's a lot of good stuff in that Xilinx Answer Database. Whenever I encounter some weird problem, I type the error message or some keywords into its search engine.
 

    no_mad

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no_mad

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modelsim error 3043

Hi,

Thanks for all the reply.

echo47, the website you gave me is very helpful.

Anyways, I have encounter new problems. When I ran my simulation, Modelsim give me this error:

# ** Error: C:/Xilinx/verilog/src/simprims/X_FF.v(55): $recovery( negedge RST:21034 ps, posedge CLK &&& (rst_clk_enable == 1):21200 ps, 404 ps );
# Time: 21200 ps Iteration: 1 Instance: /tb_htg_map/UUT/\htg/tg_cgen_ise/clk2_out_356\
# ** Error: C:/Xilinx/verilog/src/simprims/X_FF.v(55): $recovery( negedge RST:8601621034 ps, posedge CLK &&& (rst_clk_enable == 1):8601621200 ps, 404 ps );
# Time: 8601621200 ps Iteration: 1 Instance: /tb_htg_map/UUT/\htg/tg_cgen_ise/clk2_out_356\
# ** Error: C:/Xilinx/verilog/src/simprims/X_FF.v(55): $recovery( negedge RST:8813621034 ps, posedge CLK &&& (rst_clk_enable == 1):8813621200 ps, 404 ps );
# Time: 8813621200 ps Iteration: 1 Instance: /tb_htg_map/UUT/\htg/tg_cgen_ise/clk2_out_356\

FYI, I already check in Xilinx website as u suggested. But no match.

How to fix recovery error for Xilinx FPGA design?
Thus, anyone of you faced this error before. Please share it, highly appreciated.

Thanx in advance,
-no_mad
 

no_mad

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modelsim for xilinx v7.1i

yup, another unhelpful error message.

Actually, I have tried search it in xilinx website. I got the same result as you. It didnt help me getting the answer tht I want.

According to the solution 1, the Verilog SimPrim error may be safely ignored.

In my opinion, it is only apply for timing simulation of a FIFO generator core in verilog. In my simulation, I tried to ignore these errors but my output signals are all 'X'.

I think I need to find a solution for reset removal and recovery for FPGA design.

What do you think? :)

-no_mad
 

echo47

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modelsim simulation issue

Can you show us a small example project that produces the error? Maybe someone can see the problem, or at least try it on different versions of ISE and ModelSim. If you don't have the latest versions (7.1.04i and 6.1c), try updating them, especially ISE.

My X_FF.v file doesn't have any $recovery statements.

Maybe submit a Xilinx support WebCase, if you have a support arrangement.
 

no_mad

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too many port connection modelsim

Hi echo47,

Finally, my problem have been solved. Like I’ve told you earlier, the root cause of this error is my reset signal violate recovery time.

Therefore I make my reset signal triggered earlier than the rising edge of my clock.

FYI, I’m using asynchronous reset signal. Now, I have more questions.

Will I be facing this problem again when I implement it on FPGA? Do I need reset synchronizer circuit to solve this issue?

Please enlighten me

-no_mad
 

echo47

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modelsim rising edge

Asynchronous reset can cause a lot of trouble in synchronous systems. I don't know why so many FPGA books and tutorials teach such a poor concept. If my project needs an external reset, I use synchronous reset. However, most of my projects are self-synchronizing, so they don't need any reset at all.
 

leyuanniao

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modelsim bug asynchrone

I think it's necessary using a reset synchronizer circuit for asynchronous reset.
And I see a solusition suggestiong for Virtex.

https://china.xilinx.com/support/answers/23298.htm

"Xilinx recommends that the RST signal be synchronized in the ISERDES or OSERDES CLK or CLKDIV domain to avoid any violation of the recovery or removal times."
 

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