help in type conversion in vhdl

[nastarans]

hi im new in vhdl and hope somebody can help me
i have problem in type conversion in vhdl from nemeric to array for example is this code correct?
product:= routing(0)*rulevaluation(0)+routing(1)*rulevaluation(1)+routing(2)*rulevaluation(2)+routing(3)*rulevaluation(3)+routing(4)*rulevaluation(4)
routing and rulevaluation is array and product is real
Thank you for your help

 

[FvM]

"array" allone isn't a type. Please post the full type or signal definition.

In addition, real isn't a synthesizable VHDL type, it's only provided for internal calculations in simulator testbenches.

 

[iamnoori]

Hi.I think its betther that u define your signals and variables with "unsigned" type,and use the "nemeric" library.

 

[omidsht]

real is not synthesizable , you can use ipcores for fixed or float math.