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[SOLVED] help in file handling in vhdl

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chaitanya.531

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i want to write output into a file in hard disk
plz heelp meee
 

How far have you got?
I assume you want this for a testbench (File IO is not appropriate for synthesis on an FPGA).
 

plz

what i want is i have a program in vhdl i want to take "out put "into a hard disk file (.dat)
WHY File IO is not appropriate for synthesis on an FPGA
Code: 
LIBRARY	IEEE;
USE	IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


ENTITY key_exp IS
    PORT
    (
        clr : IN STD_LOGIC;
        clk	: IN STD_LOGIC;
        key_in	: IN STD_LOGIC;
        ukey	: IN STD_LOGIC_VECTOR(127 DOWNTO 0);
        skey_0	: out STD_LOGIC_VECTOR (31 DOWNTO 0);
        skey_1	: out STD_LOGIC_VECTOR (31 DOWNTO 0);
		  skey_2	: out STD_LOGIC_VECTOR (31 DOWNTO 0);
		  skey_3	: out STD_LOGIC_VECTOR (31 DOWNTO 0);
		  skey_4	: out STD_LOGIC_VECTOR (31 DOWNTO 0);
        skey_5	: out STD_LOGIC_VECTOR (31 DOWNTO 0);
        skey_6	: out STD_LOGIC_VECTOR (31 DOWNTO 0);
		  skey_7	: out STD_LOGIC_VECTOR (31 DOWNTO 0);
        skey_8	: out STD_LOGIC_VECTOR (31 DOWNTO 0);
        skey_9	: out STD_LOGIC_VECTOR (31 DOWNTO 0);
        skey_10: out STD_LOGIC_VECTOR (31 DOWNTO 0); 
        skey_11: out STD_LOGIC_VECTOR (31 DOWNTO 0);
        skey_12: out STD_LOGIC_VECTOR (31 DOWNTO 0);
        skey_13: out STD_LOGIC_VECTOR (31 DOWNTO 0);
        skey_14: out STD_LOGIC_VECTOR (31 DOWNTO 0);
		  skey_15: out STD_LOGIC_VECTOR (31 DOWNTO 0);
		  skey_16: out STD_LOGIC_VECTOR (31 DOWNTO 0);
		  skey_17: out STD_LOGIC_VECTOR (31 DOWNTO 0);
        skey_18: out STD_LOGIC_VECTOR (31 DOWNTO 0);
        skey_19: out STD_LOGIC_VECTOR (31 DOWNTO 0);
		  skey_20	: out STD_LOGIC_VECTOR (31 DOWNTO 0);
        skey_21	: out STD_LOGIC_VECTOR (31 DOWNTO 0);
        skey_22	: out STD_LOGIC_VECTOR (31 DOWNTO 0);
        skey_23	: out STD_LOGIC_VECTOR (31 DOWNTO 0); 
        skey_24	: out STD_LOGIC_VECTOR (31 DOWNTO 0);
        skey_25	: out STD_LOGIC_VECTOR (31 DOWNTO 0);
        key_rdy	: OUT STD_LOGIC
    );
END key_exp;


architecture Behavior  of key_exp is
    
    signal i_cnt : std_logic_vector(4 downto 0);
    signal j_cnt : std_logic_vector (1 downto 0);
    signal k_cnt : std_logic_vector (6 downto 0);
    signal a_tmp1:std_logic_vector (31 downto 0);
  -- A registers 
	 signal a_tmp2 : std_logic_vector (31 downto 0);
    signal a_reg  : std_logic_vector (31 downto 0);
  -- B registers
    signal b_tmp1 : std_logic_vector (31 downto 0);
    signal b_tmp2 : std_logic_vector (31 downto 0);
    signal b_reg : std_logic_vector (31 downto 0);
    
    signal ab_tmp : std_logic_vector(31 downto 0);
   
    TYPE   S_ARRAY IS ARRAY (0 TO 25) OF STD_LOGIC_VECTOR (31 DOWNTO 0);
    TYPE   L_ARRAY IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR (31 DOWNTO 0);
    TYPE     StateType IS (ST_IDLE, ST_KEY_IN, ST_KEY_EXP, ST_READY);
    
    SIGNAL	state : StateType;
	 signal  s_arr_tmp: S_ARRAY;
    signal  l_arr : L_ARRAY;
    signal  keyrdy :std_logic;
    type  rom is array (0 to 25) of std_logic_vector (31 downto 0);
    signal   s_key_tmp : rom;
    begin
    
    a_tmp1 <= s_arr_tmp(conv_integer(i_cnt)) + a_reg + b_reg;
-- LEFT ROTATE BY 3
    a_tmp2<=a_tmp1(28 DOWNTO 0) & a_tmp1(31 DOWNTO 29); 
    ab_tmp<=a_tmp2 + b_reg;
    b_tmp1<=l_arr(conv_integer(j_cnt)) + ab_tmp;

WITH ab_tmp(4 DOWNTO 0) SELECT
  b_tmp2<= 
   b_tmp1(30 DOWNTO 0) & b_tmp1(31) WHEN "00001",
   b_tmp1(29 DOWNTO 0) & b_tmp1(31 DOWNTO 30) WHEN "00010",
   b_tmp1(28 DOWNTO 0) & b_tmp1(31 DOWNTO 29) WHEN "00011",
   b_tmp1(27 DOWNTO 0) & b_tmp1(31 DOWNTO 28) WHEN "00100",
   b_tmp1(26 DOWNTO 0) & b_tmp1(31 DOWNTO 27) WHEN "00101",
   b_tmp1(25 DOWNTO 0) & b_tmp1(31 DOWNTO 26) WHEN "00110",
   b_tmp1(24 DOWNTO 0) & b_tmp1(31 DOWNTO 25) WHEN "00111",
   b_tmp1(23 DOWNTO 0) & b_tmp1(31 DOWNTO 24) WHEN "01000",
   b_tmp1(22 DOWNTO 0) & b_tmp1(31 DOWNTO 23) WHEN "01001",
   b_tmp1(21 DOWNTO 0) & b_tmp1(31 DOWNTO 22) WHEN "01010",
   b_tmp1(20 DOWNTO 0) & b_tmp1(31 DOWNTO 21) WHEN "01011",
   b_tmp1(19 DOWNTO 0) & b_tmp1(31 DOWNTO 20) WHEN "01100",
   b_tmp1(18 DOWNTO 0) & b_tmp1(31 DOWNTO 19) WHEN "01101",
   b_tmp1(17 DOWNTO 0) & b_tmp1(31 DOWNTO 18) WHEN "01110",
   b_tmp1(16 DOWNTO 0) & b_tmp1(31 DOWNTO 17) WHEN "01111",
   b_tmp1(15 DOWNTO 0) & b_tmp1(31 DOWNTO 16) WHEN "10000",
   b_tmp1(14 DOWNTO 0) & b_tmp1(31 DOWNTO 15) WHEN "10001",
   b_tmp1(13 DOWNTO 0) & b_tmp1(31 DOWNTO 14) WHEN "10010",
   b_tmp1(12 DOWNTO 0) & b_tmp1(31 DOWNTO 13) WHEN "10011",
   b_tmp1(11 DOWNTO 0) & b_tmp1(31 DOWNTO 12) WHEN "10100",
   b_tmp1(10 DOWNTO 0) & b_tmp1(31 DOWNTO 11) WHEN "10101",
   b_tmp1(9 DOWNTO 0) & b_tmp1(31 DOWNTO 10) WHEN "10110",
   b_tmp1(8 DOWNTO 0) & b_tmp1(31 DOWNTO 9) WHEN "10111",
   b_tmp1(7 DOWNTO 0) & b_tmp1(31 DOWNTO 8) WHEN "11000",
   b_tmp1(6 DOWNTO 0) & b_tmp1(31 DOWNTO 7) WHEN "11001",
   b_tmp1(5 DOWNTO 0) & b_tmp1(31 DOWNTO 6) WHEN "11010",
   b_tmp1(4 DOWNTO 0) & b_tmp1(31 DOWNTO 5) WHEN "11011",   
   b_tmp1(3 DOWNTO 0) & b_tmp1(31 DOWNTO 4) WHEN "11100",
   b_tmp1(2 DOWNTO 0) & b_tmp1(31 DOWNTO 3) WHEN "11101",
   b_tmp1(1 DOWNTO 0) & b_tmp1(31 DOWNTO 2) WHEN "11110",
   

   b_tmp1(0) & b_tmp1(31 DOWNTO 1)   WHEN "11111",
   b_tmp1   WHEN OTHERS;

-- STATE MACHINE

  PROCESS(clr, clk)	  
     BEGIN
       IF(clr='0') THEN
           state<=ST_IDLE;
       ELSIF(clk'EVENT AND clk='1') THEN
           CASE state IS
              WHEN ST_IDLE =>
                  	IF(key_in='1') THEN  state<=ST_KEY_IN; keyrdy <= '0' ; END IF;
              WHEN ST_KEY_IN=> 
		state<=ST_KEY_EXP; 
      keyrdy <= '0'; 
              WHEN ST_KEY_EXP=> 
		IF(k_cnt="1001101") THEN 
      state<=ST_READY; 
         END IF;
              WHEN ST_READY =>  
       keyrdy <='1';      
       

          END CASE;
        END IF;
  END PROCESS;            


-- A REGISTER

    PROCESS(clr, clk)  BEGIN 
        IF(clr='0') THEN
           a_reg <= (others => '0');
        ELSIF(clk'EVENT AND clk='1') THEN
           IF(state=ST_KEY_EXP) THEN   a_reg<=a_tmp2;
           END IF;
        END IF;
    END PROCESS;
    
    
    -- B register
    PROCESS(clr, clk)  BEGIN
        IF(clr='0') THEN
           b_reg <= (others => '0');
			  ELSIF(clk'EVENT AND clk='1') THEN
           IF(state=ST_KEY_EXP) THEN   b_reg<=b_tmp2;
           END IF;
        END IF;
    END PROCESS;   


 --  MOD 26 COUNTER

PROCESS(clr, clk)   
 BEGIN
    IF(clr='0') THEN  i_cnt<="00000";
    ELSIF(clk'EVENT AND clk='1') THEN
       IF(state=ST_KEY_EXP) THEN
         IF(i_cnt="11001") THEN   i_cnt<="00000";
         ELSE   i_cnt<=i_cnt+1;
         END IF;
       END IF;
    END IF;
 END PROCESS;


-- MOD 4 COUNTER
PROCESS(clr, clk) 
 BEGIN
    IF(clr='0') THEN  j_cnt<="00";
    ELSIF(clk'EVENT AND clk='1') THEN
       IF(state=ST_KEY_EXP) THEN
         IF(j_cnt="11") THEN   j_cnt<="00";
         ELSE   j_cnt<=j_cnt+1;
         END IF;
       END IF;
    END IF;
 END PROCESS;
 
 process (clr,clk)  --counter
     begin
         if(clr='0') then k_cnt<="0000000";
         elsif(clk'EVENT AND clk='1') THEN
             IF(state=ST_KEY_EXP)THEN
                 IF(k_cnt="1001101") then k_cnt<="0000000";
                 ELSE k_cnt<=k_cnt+1;
             end if;
         end if;
     end if;
 end process;            
             
 
 PROCESS(clr, clk)  
 BEGIN
   IF(clr='0') THEN	 -- After system reset, S array is initialized with P and Q
      s_arr_tmp(0) <= x"b7e15163"; 
      s_arr_tmp(1) <= x"5618cb1c";
		s_arr_tmp(2) <= x"f45044d5";
		s_arr_tmp(3) <= x"9287be8e";
		s_arr_tmp(4) <= x"30bf3847";
		s_arr_tmp(5) <= x"cef6b200";
		s_arr_tmp(6) <= x"6d2e2bb9";
		s_arr_tmp(7) <= x"0b65a572";
		s_arr_tmp(8) <= x"a99d1f2b";
		s_arr_tmp(9) <= x"47d498e4";
		s_arr_tmp(10)<= x"e60c129d";
		s_arr_tmp(11)<= x"84438c56";
		s_arr_tmp(12)<= x"227b060f";
		s_arr_tmp(13)<= x"c0b27fc8";
		s_arr_tmp(14)<= x"5ee9f981";
		s_arr_tmp(15)<= x"fd21733a";
		s_arr_tmp(16)<= x"9b58ecf3";
		s_arr_tmp(17)<= x"399066ac";
		s_arr_tmp(18)<= x"d7c7e065";
		s_arr_tmp(19)<= x"75ff5a1e";
		s_arr_tmp(20)<= x"1436d3d7";
		s_arr_tmp(21)<= x"b26e4d90";
		s_arr_tmp(22)<= x"50a5c749";
		s_arr_tmp(23)<= x"eedd4102";
		s_arr_tmp(24)<= x"8d14babb";
		s_arr_tmp(25)<= x"2b4c3474";
		
   ELSIF(clk'EVENT AND clk='1') THEN
     IF(state=ST_KEY_EXP) THEN   s_arr_tmp(conv_integer(i_cnt)) <= a_tmp2;
     END IF;
   END IF;
 --  end if;
 END PROCESS;
				 s_key_tmp(0)  <= s_arr_tmp(0);
             s_key_tmp(1)  <= s_arr_tmp(1);
		       s_key_tmp(2)  <= s_arr_tmp(2);
		       s_key_tmp(3)  <= s_arr_tmp(3);
				 s_key_tmp(4)  <= s_arr_tmp(4);
             s_key_tmp(5)  <= s_arr_tmp(5);
			    s_key_tmp(6)  <= s_arr_tmp(6);
             s_key_tmp(7)  <= s_arr_tmp(7);
		       s_key_tmp(8)  <= s_arr_tmp(8);
		       s_key_tmp(9)  <= s_arr_tmp(9);
			 	 s_key_tmp(10) <= s_arr_tmp(10);
             s_key_tmp(11) <= s_arr_tmp(11);
             s_key_tmp(12) <= s_arr_tmp(12);
             s_key_tmp(13) <= s_arr_tmp(13);
		       s_key_tmp(14) <= s_arr_tmp(14);
		       s_key_tmp(15) <= s_arr_tmp(15);
				 s_key_tmp(16) <= s_arr_tmp(16);
             s_key_tmp(17) <= s_arr_tmp(17);
			    s_key_tmp(18) <= s_arr_tmp(18);
             s_key_tmp(19) <= s_arr_tmp(19);
		       s_key_tmp(20) <= s_arr_tmp(20);
		       s_key_tmp(21) <= s_arr_tmp(21);
				 s_key_tmp(22) <= s_arr_tmp(22);
             s_key_tmp(23) <= s_arr_tmp(23);
           	 s_key_tmp(24) <= s_arr_tmp(24);
             s_key_tmp(25) <= s_arr_tmp(25);
PROCESS(clr, clk)
   BEGIN
     IF(clr='0') THEN
        l_arr(0)<="00000000000000000000000000000000";
          l_arr(1)<="00000000000000000000000000000000";
            l_arr(2)<="00000000000000000000000000000000";
              l_arr(3)<="00000000000000000000000000000000";
     ELSIF(clk'EVENT AND clk='1') THEN
        IF(state=ST_KEY_IN) THEN
           l_arr(0)<=ukey(31 DOWNTO 0);
          l_arr(1)<=ukey(63 DOWNTO 32);
          l_arr(2)<=ukey(95 DOWNTO 64);
          l_arr(3)<=ukey(127 DOWNTO 96);
        ELSIF(state=ST_KEY_EXP) THEN
           l_arr(conv_integer(j_cnt))<=b_tmp2;
        END IF;
     END IF;
end process;

PROCESS (keyrdy) 
BEGIN
	
		if ( rising_edge(keyrdy)) and keyrdy='1' then
			 skey_0 <= s_key_tmp(0);
			 skey_1 <= s_key_tmp(1);
			 skey_2 <= s_key_tmp(2);
			 skey_3 <= s_key_tmp(3);
			 skey_4 <= s_key_tmp(4);
			 skey_5 <= s_key_tmp(5);
			 skey_6 <= s_key_tmp(6);
			 skey_7 <= s_key_tmp(7);
			 skey_8 <= s_key_tmp(8);
			 skey_9 <= s_key_tmp(9);
			 skey_10 <= s_key_tmp(10);
			 skey_11 <= s_key_tmp(11); 
			 skey_12 <= s_key_tmp(12);
			 skey_13 <= s_key_tmp(13);
			 skey_14 <= s_key_tmp(14);
			 skey_15 <= s_key_tmp(15);
			 skey_16 <= s_key_tmp(16);
			 skey_17 <= s_key_tmp(17);
			 skey_18 <= s_key_tmp(18);
			 skey_19 <= s_key_tmp(19);
			 skey_20 <= s_key_tmp(20);
			 skey_21 <= s_key_tmp(21); 
			 skey_22 <= s_key_tmp(22);
			 skey_23 <= s_key_tmp(23);
			 skey_24 <= s_key_tmp(24);
			 skey_25 <= s_key_tmp(25);
         
			end if;
		
end process;
key_rdy <=keyrdy;
end Behavior;
 

File IO in VHDL is only for testbenching (ie. for simulation).
File IO does not map to any appropriate logic. For this you need to create a controller for whatever device you are using (and its likely to be extreamly complicated in the case of a hard disk). Its easier just to let a micro controller handle a file system.

What kind of data are you trying to output, and for what purpose?
 

its a key expansion module
subkeys are taken to a text file

yes file io in vhdl is for testbench only

that text is used for encryption module

i want testbench tutorial where explanation for the out puts taken into a text file

and file io commands
 

ya i read the pdf and try to write test bench following errors occures


Code: 
ERROR:HDLParsers:164 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 89. parse error, unexpected TOKFILE
ERROR:HDLParsers:3312 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 147. Undefined symbol 'kfp'.
ERROR:HDLParsers:1209 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 147. kfp: Undefined symbol (last report in this block)
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 147. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 149. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:164 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 150. parse error, unexpected SEMICOLON
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 151. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 153. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 155. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 157. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 159. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 161. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:164 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 162. parse error, unexpected SEMICOLON
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 163. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 165. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 167. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 169. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 171. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 173. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:164 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 174. parse error, unexpected SEMICOLON
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 175. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 177. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 179. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 181. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 183. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 185. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 187. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 189. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 191. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 193. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 195. Formal parameter L of procedure writeline must be associated with an actual value.
ERROR:HDLParsers:3326 - "C:/Xilinx/rc5soc/rc5soc/testkeyexp.vhd" Line 197. Formal parameter L of procedure writeline must be associated with an actual value.
code testbench is
Code: 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use STD.TEXTIO.all;
use IEEE.STD_LOGIC_TEXTIO.all;
ENTITY testkeyexp_vhd IS
END testkeyexp_vhd;

ARCHITECTURE behavior OF testkeyexp_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT key_exp
   generic (
             outfile  : string := "C:\Xilinx\rc5soc\rc5soc\rc5_encrypt_tb.key"
          );
	PORT(
		clr : IN std_logic;
		clk : IN std_logic;
		key_in : IN std_logic;
		ukey : IN std_logic_vector(127 downto 0);          
		skey_0 : OUT std_logic_vector(31 downto 0);
		skey_1 : OUT std_logic_vector(31 downto 0);
		skey_2 : OUT std_logic_vector(31 downto 0);
		skey_3 : OUT std_logic_vector(31 downto 0);
		skey_4 : OUT std_logic_vector(31 downto 0);
		skey_5 : OUT std_logic_vector(31 downto 0);
		skey_6 : OUT std_logic_vector(31 downto 0); 
		skey_7 : OUT std_logic_vector(31 downto 0);
		skey_8 : OUT std_logic_vector(31 downto 0);
		skey_9 : OUT std_logic_vector(31 downto 0);
		skey_10 : OUT std_logic_vector(31 downto 0);
		skey_11 : OUT std_logic_vector(31 downto 0);
		skey_12 : OUT std_logic_vector(31 downto 0);
		skey_13 : OUT std_logic_vector(31 downto 0);
		skey_14 : OUT std_logic_vector(31 downto 0);
		skey_15 : OUT std_logic_vector(31 downto 0);
		skey_16 : OUT std_logic_vector(31 downto 0);
		skey_17 : OUT std_logic_vector(31 downto 0);
		skey_18 : OUT std_logic_vector(31 downto 0);
		skey_19 : OUT std_logic_vector(31 downto 0);
		skey_20 : OUT std_logic_vector(31 downto 0);
		skey_21 : OUT std_logic_vector(31 downto 0);
		skey_22 : OUT std_logic_vector(31 downto 0);
		skey_23 : OUT std_logic_vector(31 downto 0);
		skey_24 : OUT std_logic_vector(31 downto 0);
		skey_25 : OUT std_logic_vector(31 downto 0);
		key_rdy : OUT std_logic

		);
	END COMPONENT;

	--Inputs
	SIGNAL clr :  std_logic := '0';
	SIGNAL clk :  std_logic := '0';
	SIGNAL key_in :  std_logic := '0';
	SIGNAL ukey :  std_logic_vector(127 downto 0) := (others=>'0');

	--Outputs
	SIGNAL skey_0 :  std_logic_vector(31 downto 0);
	SIGNAL skey_1 :  std_logic_vector(31 downto 0);
	SIGNAL skey_2 :  std_logic_vector(31 downto 0);
	SIGNAL skey_3 :  std_logic_vector(31 downto 0);
	SIGNAL skey_4 :  std_logic_vector(31 downto 0);
	SIGNAL skey_5 :  std_logic_vector(31 downto 0);
	SIGNAL skey_6 :  std_logic_vector(31 downto 0);
	SIGNAL skey_7 :  std_logic_vector(31 downto 0);
	SIGNAL skey_8 :  std_logic_vector(31 downto 0);
	SIGNAL skey_9 :  std_logic_vector(31 downto 0);
	SIGNAL skey_10 :  std_logic_vector(31 downto 0);
	SIGNAL skey_11 :  std_logic_vector(31 downto 0);
	SIGNAL skey_12 :  std_logic_vector(31 downto 0);
	SIGNAL skey_13 :  std_logic_vector(31 downto 0);
	SIGNAL skey_14 :  std_logic_vector(31 downto 0);
	SIGNAL skey_15 :  std_logic_vector(31 downto 0);
	SIGNAL skey_16 :  std_logic_vector(31 downto 0);
	SIGNAL skey_17 :  std_logic_vector(31 downto 0);
	SIGNAL skey_18 :  std_logic_vector(31 downto 0);
	SIGNAL skey_19 :  std_logic_vector(31 downto 0);
	SIGNAL skey_20 :  std_logic_vector(31 downto 0);
	SIGNAL skey_21 :  std_logic_vector(31 downto 0);
	SIGNAL skey_22 :  std_logic_vector(31 downto 0);
	SIGNAL skey_23 :  std_logic_vector(31 downto 0);
	SIGNAL skey_24 :  std_logic_vector(31 downto 0);
	SIGNAL skey_25 :  std_logic_vector(31 downto 0);
	SIGNAL key_rdy :  std_logic;
CONSTANT clk_period : time := 10 ns;
BEGIN
file kfp : text open write_mode is keyfile;
	-- Instantiate the Unit Under Test (UUT)
	uut: key_exp PORT MAP(
		clr => clr,
		clk => clk,
		key_in => key_in,
		ukey => ukey,
		skey_0 => skey_0,
		skey_1 => skey_1,
		skey_2 => skey_2,
		skey_3 => skey_3,
		skey_4 => skey_4,
		skey_5 => skey_5,
		skey_6 => skey_6,
		skey_7 => skey_7,
		skey_8 => skey_8,
		skey_9 => skey_9,
		skey_10 => skey_10,
		skey_11 => skey_11,
		skey_12 => skey_12,
		skey_13 => skey_13,
		skey_14 => skey_14,
		skey_15 => skey_15,
		skey_16 => skey_16,
		skey_17 => skey_17,
		skey_18 => skey_18,
		skey_19 => skey_19,
		skey_20 => skey_20,
		skey_21 => skey_21,
		skey_22 => skey_22,
		skey_23 => skey_23,
		skey_24 => skey_24,
		skey_25 => skey_25,
		key_rdy => key_rdy
	);
	clk_process :PROCESS
   begin
        clk <= '0';
        wait for clk_period/2;  --for 5 ns signal is '0'.
        clk <= '1';
        wait for clk_period/2;  --for next 5 ns signal is '1'.
   end process;
	tb : PROCESS
	BEGIN
       key_in <= '0';
		 
		-- Wait 100 ns for global reset to finish
		wait for 100 ns;
       key_in <= '1';
       clr <= '1';
        ukey <= x"12345678901234567890123456789012";		 
		 
		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;
   
   text :PROCESS 
    variable L : line;
	
   BEGIN
	 wait until key_rdy ='1';
    for i in 0 to 25 loop
	 write(L,skey_0); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_1); writeline(kfp,L);
	 wait for 1ns;;
	 write(L,skey_2); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_3); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_4); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_5); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_6); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_7); writeline(kfp,L);
	 wait for 1ns;;
	 write(L,skey_8); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_9); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_10); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_11); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_12); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_13); writeline(kfp,L);
	 wait for 1ns;;
	 write(L,skey_14); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_15); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_16); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_17); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_18); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_19); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_20); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_21); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_22); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_23); writeline(kfp,L);
	 wait for 1ns;
	 write(L,skey_24); writeline(kfp,L);	
    wait for 1ns;
	 write(L,skey_25); writeline(kfp,L);	
 end loop ;
  END PROCESS;
END;
 
Last edited by a moderator:

files need to be opened in a process, not in side the architecture.
 

Please be clearer with your posts.
If you have errors, Post what the errors are, along with the code causing the problem.
 

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