help in design of memory block

[Prabha Murugesan]

i need to design memory blocks. there are two memory blocks. when one memory block is being written ,the oter one is read and viceversa. when sel is 1 write enable of 1st memory is active. During this period the input is written in 1st memory as it receives the write address. simultaneously data is read from 2nd memory as it supplied with read address. The status of sel signal is changed to swap the read and write operation. I have enclosed the coding beloe

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity memblk is
    Port ( d : in  STD_LOGIC_VECTOR (7 downto 0);
           we : in  STD_LOGIC;
           addr : integer;
           o : out  STD_LOGIC_VECTOR (7 downto 0));
end memblk;
 
architecture Behavioral of memblk is
 
begin
type lxn is array (0 to 255) of std_logic_vector(7 downto 0);  
signal tem: lxn:=("00000001","00000010","00000011","00000100",
                         "00000101","00000110","00000111","00001000",
                         "00001001","00001010","00001011","00001100",
                          "00001101","00001110","00001111","00010000",
                          "00010001","00010010","00010011","00010100",
                          "00010101","00010110","00010111","00011000",
                          "00011001","00011010","00011011","00011100",
                          "00011101","00011110","00011111","00100000",
                          "ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ",
                          "ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ",
                          "ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ","ZZZZZZZZ",
                           others=>"ZZZZZZZZ");
 
process(d,we,addr)
begin
if(we='0')then
tem(addr)<=d;
else
o<=tem(addr);
end if;
end process;
end Behavioral;

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i got following errors
ERROR:HDLParsers:164 - "C:/Xilinx/PRABHU/memblk.vhd" Line 40. parse error, unexpected TYPE
ERROR:HDLParsers:3313 - "C:/Xilinx/PRABHU/memblk.vhd" Line 57. Undefined symbol 'tem'. Should it be: em or rem?
ERROR:HDLParsers:1209 - "C:/Xilinx/PRABHU/memblk.vhd" Line 57. tem: Undefined symbol (last report in this block)

 

[TrickyDicky]

all declarations (types, signals etc) need to be before the begin on the architecture.

PS. THis code will not infer a RAM, as it is asynchronous. It will use logic to emulate your Ram.