[SOLVED] help in debugging fsm functionality in vhdl

[rakeshk.r]

HI , I have 3 states, 's0' to initialize the values and 's1' to count and stay untill it reaches value 4 and move to stop state 's2' when it reaches 5. The problem here is that the entire count finishes in 1 clock edge rather i wanted each count to happen on each rising edge of clock untill it reaches value 5. How to fix this. since my other components are synchronous design. I wanted my fsm too be synchronous to clock. Below I have the design code, snippet of my testbench and output waveform of the fsm design. Thank you.

 LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY test_hdl IS
port  ( clk : IN std_logic;
        rst : IN std_logic; 
        en  : IN std_logic;
        output : OUT std_logic
      );
        
END ENTITY test_hdl;

--
ARCHITECTURE test1 OF test_hdl IS
signal itr : unsigned  (12 downto 0);
signal en_out : std_logic;
type STATE_TYPE is (s0, s1, s2);
signal PRESENT_STATE:  STATE_TYPE;
signal NEXT_STATE: STATE_TYPE;

BEGIN

STATE_proc: process (clk)
begin
if rising_edge(clk) then 
         if (rst='0') then 
		      
     	       PRESENT_STATE <= NEXT_STATE;
         else 
             PRESENT_STATE <= s0;  
             
        end if; -- rst 
end if;       
end process STATE_proc; 

comb_proc: process(PRESENT_STATE,en,itr)
variable itr_reg : unsigned(12 downto 0);
variable reg1 : integer range 0 to 10;
begin
case PRESENT_STATE is 
when s0 => 
        if en = '1' then 
             
          NEXT_STATE <= s1;
        else 
          NEXT_STATE <= s0;
        end if;
        itr_reg := (others=>'0');
        itr <= (others=>'0');
        reg1 := 0;
        en_out <= '0';
        output <= '0'; 
         
  when s1 => 
        if en='1' then 
                      
            if itr_reg < 5 then 
               itr_reg := itr;
               itr <= itr_reg + 1;
               NEXT_STATE <= s1;
               output <= '1';
               en_out <= '1';
            else 
               NEXT_STATE <= s2;  
               itr <= (others=>'0');
               output <= '0'; 
               en_out <= '0';           
            end if;
         else 
            NEXT_STATE <= s0;
            output <= '0'; 
         end if;
         reg1 := to_integer(itr_reg);
                       
  when s2 => 
      
       if en = '1' then  
         NEXT_STATE <= s2;              
       else 
         NEXT_STATE <= s0;
       end if; 
       output <= '0';  
       en_out <= '0';   
       itr <= (others=>'0');             
       itr_reg := (others=>'0');             
end case;     
end process comb_proc; 
END ARCHITECTURE test1;

-- Test Bench --- 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

LIBRARY project_lib;

ENTITY tb_test_hdl IS
END ENTITY tb_test_hdl;


ARCHITECTURE arch OF tb_test_hdl IS
-- internal signal 
signal clk_tb   : std_logic := '0'; 
signal rst_tb   : std_logic := '1';
signal en_tb   : std_logic := '0';
signal out_tb   : std_logic;
constant clk_period : time := 10 ns;  

-- component instantiation
component test_hdl
  
  port(
      clk   : IN     std_logic;
      rst   : IN   std_logic;
      en    : IN std_logic;
      output: OUT   std_logic
      );
end component;

For all : test_hdl use entity project_lib.test_hdl; 

BEGIN
-- instantiate the Unit Under Test 
   uut:test_hdl port map(
        clk => clk_tb,
        rst => rst_tb,
        en  => en_tb,
        output => out_tb
      );

clk_toggle:process
begin
  clk_tb <= '1';
  wait for clk_period/2;  -- for 5 ns clk is 'low'.
  clk_tb <= '0';
  wait for clk_period/2;  -- for next 5 ns clk is 'high'.  
end process;

sim_tb: process
begin
  rst_tb <= '1';
  en_tb <= '0';
  wait for 10 ns;
  en_tb <= '1';
  rst_tb <= '0';
  wait for 100 ns;
  en_tb <= '0';
wait;
end process;  
END ARCHITECTURE arch;

 

[ruchibora]

I wonder how your code compile ... There are errors in your code....where is the beginning of combo logic ??

 

[rakeshk.r]

oops sorry about that. Now I have edited the starting part of combo logic . Thanks for letting me know.

 

[ruchibora]

your itr signal does not increment with clock, it increments when fsm is in s1 state.
Try incrementing it in seq. logic.

 

[TrickyDicky]

You also cannt create registers with variables in an async process. Thye need to be in a clocked process.