help: IIR Filter design

[Zerox100]

I want to write a second order low pass IIR filter. Could you please suggest me good tutorials and examples?

Another Q: Could i reach 300 MHz IIR with FPGA ?

 

[barry]

There's lots of stuff on the web; Look at this:**broken link removed**

300 MHz, that should be possible. I assume you mean a 300 MHz sample rate, right?

 

[FvM]

IIR with 300 MHz sample frequency means that an elementary constant multiply and add operation must be performed in one clock cycle. There's no option to use e.g. a pipelined adder. So the question refers to the performance figures of the involved FPGA family. I assume that it's possible with recent FPGAs, at least for moderate word widths.

 

[barry]

I think you can still use pipelining-you're just adding latency.

 

[FvM]

I think you can still use pipelining

I don't see how. The IIR feedback path has to be closed with 1 clock cycle delay.

 

[barry]

Hmm, I was thinking FIR. I have to think on this a bit, I haven't done much with IIRs.

 

[permute]

non-trivial IIR filters can be difficult. clearly something like y_n = a*y_{n-2} + b*x_n would be easier than the 1st order y_n = a*y_{n-1} + x_n. Likewise y_n = (y_{n-1} + y_{n-2} + x_n)/2 would be more ideal as well.

However, IIR filters are much more implementation dependent because the bit widths and quantization effects at various stages will affect the output. Likewise, the quantization of the coefficients makes implementations different. Because the speed of a simple design is limited by the speed of the multiply and ternary add path, the size of the operands is important.

 

[Aser]

I don't see how. The IIR feedback path has to be closed with 1 clock cycle delay.

If you double all the registers in the IIR filter then you can organize the pipelining.
But you get two filter channels, and a single filter cycle increases in two clock cycles,
and due to the pipelining the clock cycle can be decreased up to two times.
Therefore, the IIR filter pipelining is the real thing.
And one can get the clock frequency up to 300 MHz, but the sampling frequency will be much less.
Some exclusion is multiplierless wave digital filter, like one in https://kanyevsky.kpi.ua/Studentam/labexercise 3.pdf
which is 2-nd order IIR filter as well.

 

[FvM]

If you double all the registers in the IIR filter then you can organize the pipelining.
But you get two filter channels, and a single filter cycle increases in two clock cycles,
and due to the pipelining the clock cycle can be decreased up to two times.
Therefore, the IIR filter pipelining is the real thing.

If I understand right, you mean that you can achieve higher sampling rate by processing the data in two interleaved channels. Yes, but it's a also different filter algorithm. You can't implement an IIR filter with the same characteristic than a regular full data rate filter.

300 MHz IIR will be possible with recent programmable logic - at least for moderate word width.

CIC filters have a special purpose and aren't a solution for the problem discussed in this thread.

 

[Aser]

If I understand right, you mean that you can achieve higher sampling rate by processing the data in two interleaved channels. Yes, but it's a also different filter algorithm. You can't implement an IIR filter with the same characteristic than a regular full data rate filter.

I mean so too. The idea is that by such a pipelining the algorithm remains the same. But the hardware volume decreases for the same throughput due to the implementation of parallel channels or stages in sequence. Sometimes due to the effective retiming the clock
speed increases dramatically, and the sampling frequency can increase.

300 MHz IIR will be possible with recent programmable logic - at least for moderate word width.

I've proposed to look at the wave digital filters, which have small bit width coefficients and therefore can be implemented without multipliers. As a result, its critical paths can be very short. Some of them have 2 delays in the feedback, which is well for retiming and pipelining.
I can add that a method of speculative IIR filter representation is known, which essence is to increase the number of delays in the feedback.

CIC filters have a special purpose and aren't a solution for the problem discussed in this thread.

I don't mean CIC filters, but the integrator in it is an example of degraded IIR filter.

 

[FvM]

Simple example, first order low-pass:

y(n) = a*y(n-1) + (1-a)*x(n)

a*y(n-1) + ... is the critical path, as discussed in post #3 and #7. How to pipeline the IIR filter without affecting the original impulse response?

 

[permute]

This is probably the best I've seen thus far:
y = a*y(n-1) + (1-a)*x
y(n+1) = a*y(n-1) + (1-a)*x(n+1) = a^2*y(n-1) + a*(1-a)*x(n+1)
y(n+2) = a^3*y(n-1) + f(x)
...

notice that in an implementation, all of the terms with x's can be precomputed in an fir filter. now you are left with a system that gets a block of N outputs every N samples, but doesn't generate the outputs evenly.

 

[Zerox100]

Let consider a first order simple example. Is it possible to implement it at 300 mhz?

H(z)=a/(1-b(Z^-1))

 

[FvM]

As far as possible without a detail specification, the question is answered in post #9.

 

[Aser]

Let consider a first order simple example. Is it possible to implement it at 300 mhz?

H(z)=a/(1-b(Z^-1))

Consider the lookahead computation.
Due to the formula y(i)=ax(i)+by(i-1);
by(i-1)=abx(i-1)+bby(i-2)=cx(i-1)+dy(i-2).
The resulting equation is y(i)=ax(i)+cx(i-1)+dy(i-2).
Here you are the feed forward path as in the FIR filter -it can be implemented in 300 MHz,
and the feed back path with the twofold delay, which can be implemented in the pipelined manner in 300 MHz as well.:smile: