Zerox100
Full Member level 6
I want to write a second order low pass IIR filter. Could you please suggest me good tutorials and examples?
Another Q: Could i reach 300 MHz IIR with FPGA ?
Another Q: Could i reach 300 MHz IIR with FPGA ?
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I don't see how. The IIR feedback path has to be closed with 1 clock cycle delay.I think you can still use pipelining
If you double all the registers in the IIR filter then you can organize the pipelining.I don't see how. The IIR feedback path has to be closed with 1 clock cycle delay.
If I understand right, you mean that you can achieve higher sampling rate by processing the data in two interleaved channels. Yes, but it's a also different filter algorithm. You can't implement an IIR filter with the same characteristic than a regular full data rate filter.If you double all the registers in the IIR filter then you can organize the pipelining.
But you get two filter channels, and a single filter cycle increases in two clock cycles,
and due to the pipelining the clock cycle can be decreased up to two times.
Therefore, the IIR filter pipelining is the real thing.
I mean so too. The idea is that by such a pipelining the algorithm remains the same. But the hardware volume decreases for the same throughput due to the implementation of parallel channels or stages in sequence. Sometimes due to the effective retiming the clockIf I understand right, you mean that you can achieve higher sampling rate by processing the data in two interleaved channels. Yes, but it's a also different filter algorithm. You can't implement an IIR filter with the same characteristic than a regular full data rate filter.
I've proposed to look at the wave digital filters, which have small bit width coefficients and therefore can be implemented without multipliers. As a result, its critical paths can be very short. Some of them have 2 delays in the feedback, which is well for retiming and pipelining.300 MHz IIR will be possible with recent programmable logic - at least for moderate word width.
I don't mean CIC filters, but the integrator in it is an example of degraded IIR filter.CIC filters have a special purpose and aren't a solution for the problem discussed in this thread.
y(n) = a*y(n-1) + (1-a)*x(n)
Consider the lookahead computation.Let consider a first order simple example. Is it possible to implement it at 300 mhz?
H(z)=a/(1-b(Z^{-1}))