Help:GSM's phase eror

[rhjang]

68pf clock 26mhz

Hi all
When I measure the phase error of DCS and PCS.
If Tx power is more than 22dBm
The phase error of 0-6 bits were increase and failed, other bits were not.
I use midamble to synchronize burst, frequency is OK.
What will cause the phase error?
Please help me ><~~

 

[vfone]

gsm phase error

Bad phase error under conducted test:
-VCO pulling
-Bad PA behavior during active side of the burst. Check the Control Loop.
-Bad design of the DC trace between PA and battery (too much DC drop on the line)

Bad phase error under radiated test:
-Feedback between radiated signal from the antenna to the VCO compartment (need better shielding)

regards

 

[ttrf]

trf6151

I ASK a question,
is the DUT the handset? or base station?
if tx power is lower than 22dBm, is there no problem?
if these are true,check the control loop or the pa supply.

 

[mckinson]

gsm phase error

I think , the reference clock (13m) is interfaced. Pls check !!~

 

[rhjang]

gsm phase error layout

Hi all:
Thank your kindly reply.
I measured handset under conducted condition.
My PA is RFMD's RF3133, integrated with power control.
So I think the control loop is OK.

I checked DC drop on power line.(PA and transceiver use the same power line)
It's about 135mV drop down during burst, but GSM 900 have more DC drop and GSM 900 pass the phase and frequency error.
I try to connect power line near PA with 1uF to 10uF to GND, there is no improve, I also conect with 12p and 47p to decouple 900 and 1800.1900 interference.
Can I exclude the DC drop issue?

 

[rhjang]

gsm phase error layout

I think , the reference clock (13m) is interfaced. Pls check !!~

Hi mckinson
Do you mean the reference clock is interferenced?
I have a question.
If the reference clock is interferenced, why only the first 6 bits was affected but not all bits?
The system use 26MHz reference clock and series with a 68pF to reduce noise on the vcxo core supply.
I used oscilloscope to check the clock under PCS power level 0 and 5, there is no differernt under level 0 and 5, but the phase will fail under power level 0.

 

[rhjang]

help gsm phase error

Bad phase error under conducted test:
-VCO pulling
-Bad PA behavior during active side of the burst. Check the Control Loop.
-Bad design of the DC trace between PA and battery (too much DC drop on the line)

Bad phase error under radiated test:
-Feedback between radiated signal from the antenna to the VCO compartment (need better shielding)

regards

Hi vfone

How to check VCO pulling?
The 26MHz VCXO is integrated into the tansceiver, use external 26MHz crystal and a tank circuit with a varactor.

Although I measured under conducted condition.
Maybe there is feedback from PA outout to crystal.
But I still have two question:
1.GSM 900's highest power(33dBm) is more than DCS and PCS(30dBm), why there is no feedback?
2.Why only first 6 bits were affected but not all bits?

 

[xinxin]

Hi , rhjang

I also use the RF3133 PA , and met this problem as you talk about , but this problem occurs at the upper power . pls check your layout , especially rf out from PA to switch .After we relayout about rf out , this problem improves , but still exists.but could u tell me why put a cap. series with VCOVCC ? Which solution do you take ? We could contact each other about RF experiences in the future , couln't we?

 

[rhjang]

Hi , rhjang

I also use the RF3133 PA , and met this problem as you talk about , but this problem occurs at the upper power . pls check your layout , especially rf out from PA to switch .After we relayout about rf out , this problem improves , but still exists.but could u tell me why put a cap. series with VCOVCC ? Which solution do you take ? We could contact each other about RF experiences in the future , couln't we?

Hi xinxin:

It's very exciting that someone met the same problem!!
Does the upper power means higher power or power level?(lower power level has higher power)
I use TI's RITA(TRF6151) as my transceiver.
At the Xin pin, TI recommend to series a filtering capacitor to reduce noise.
Can I ask what did you change in layout and the reason, how much were improved?
I checked the layout it seems part of PA DCS out line is too closer to 3133's VCCOUT power line, will this cause th phase error at the beging of burst?

regards

 

[vfone]

Definitely you have a feed-back from the output of the PA to the input. Why is happened at low power? Because at low power a GSM/DCS PA has the maximum gain. At full power is in compression. DCS PA is more sensitive to this phenomenon than GSM PA. Check the layout design.
135mV DC drop during the burst for DCS is too much, even if the phase error is ok. You lose efficiency.
regards

 

[xinxin]

Good morning , rhjiang

What vfone said is very right , you could reroute your rf out line , especially DCS/PCS line. and you must pay more attation to your PA input and output layout , that's to say lower power and higher power. and shorten your PCS/DCS line as soon as possible.

 

[xinxin]

rhjiang , are you in china now ? which city do u work?

 

[rhjang]

Hi xinxin,
Sorry, I'm not in china.
Did you add PA shielding, I added shielding to PA and the phase error improved obviously.

vfone,
If the phase error is caused by feed-back from the output of the PA to the input, why just the beging of burst were afected?
Is there any inference or theory, or just experience?

And there is a strangh phenomenon.
There are many compoment too close to PA so I can't shield PA prefectly, one of four side PA shielding is not soldered but the gap of shielding case to GND is less than 0.5mm.
It seems that DCS and PCS signal still radiated, is 0.5mm too much for DCS and PCS signal?
I tried use finger to touch the shielding side which is not soldered, nothing changed.
But when I touch the shielding side which is not soldered and the SMA connector's GND(I use this SMA to connect antenna or test equipment), the phase error were improved obviously.
Does this means the GND of the PA and SMA connector were not connect prefectly?

 

[mckinson]

I think the roader of VCO output is no matching ,so the signal feed back to the VCO ,cause the VCO frequency pulling . Try triming the impedance of VCO output.

 

[xinxin]

I think this size of the hole on the shielding case is very important for improve the phase error , and hole lacation is also too. of course the GND of shielding case connected the main GND need to be cared .

 

[mckinson]

I have met this problem ,but not solution yet.I try many way ,for example shelding ,decoupling ..but no usefull .I think the impedance of PA output is no mathing ,but not try. I think I must change my layout .Anybody know how can I do ?

 

[rhjang]

Hi mckinson,

I think PA output matching is not the main reason of the phase error, it affect the output power.

 

[rhjang]

I add a shielding to PA and the phase error pass the GSM spec, but the phase error at the beging of the burst still exist.

Someone told me that WLAN use ARM to adjust IQ signal to eliminate phase error, I think the IQ structure of GSM and WLAN are the same, does GSM's baseband have the function to finetune IQ signal to eliminate the phase error?

 

[mckinson]

The reason of phase error is too much.
I think the I/Q is the one of them .If I/Q signal is interfered, I think that would cause the phase error

 

[martinthorn]

GSM's baseband have the function to finetune IQ signal to eliminate the phase error?

Some GSM basebands can finetune IQ phase and amplitude to remove
imbalances at the modulator caused by poor LO phase balance and
modulator imperfections. This is done to improve unwanted sideband
level (seen in all '1' or '0's modulation) and LO breakthrough. Note
that this is not the cause of your problem because a poorly balanced
IQ modulator would give bad phase error throughout all the burst.

I have seen poor phase error at the start of bursts often during
phone development. In GSM phones the phase error in DCS/PCS is
usually worse in 4GHz direct conversion tranceivers because the
PA 2nd harmonic is much stronger than the 4th harmonic (GSM900).
So VCO pulling effect is stronger at DCS/PCS bands hence your
problem is worst there. The solution is most likely in the PCB layout :
route sensitive tracks carefully and use many ground vias for
stitching around RF tracks and placed close to decoupling capacitors.

2.Why only first 6 bits were affected but not all bits?

Possible answers :
First bits of the burst are the same. This means that the PA harmonic
output is at a fixed freq offset compared to VCO freq : pulling is constant
and in the same direction. After these bits the burst data is random so
the pulling is not so severe in any one direction. There is also possibly
some pulling occurring due to ground currents under the rf asic as the
PA burst ramps up.

Another explanation (though almost certainly not the cause of your problem)
is that the PLL could be switching to the burst frequency too late. This
would mean that the PLL is still settling to freq as the burst starts. This
would give a phase error reading at the start of the burst. This is probably
not the cause of your problem because shielding helped you. Only
software would fix this problem (or a change of PLL bandwidth).

Martin