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[Help]FPGA resource utilization going above 100%

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mtechvlsi007

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Tried in almost all FPGA boards, but FPGA resource utilization going above 100%.
Actually I'm storing about 200 thirty two bit (32 bit) values in each array.So resource utilization is going above 100%.
Is there any way to initialize all these values to a memory , so I can access in any time? Thereby I want to reduce resource utilization.
Code:
module trial(out0,out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,sel,clk,rst);
input clk,rst;
input [3:0] sel;
output [31:0] out0,out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14;
wire en;
reg rst_1;
//wire [31:0] test [3:0] [10:0];
reg [31:0] in [10:0];
//wire [31:0] in1 [9:0];
//wire [31:0] tar [3:0] [10:0];
//reg [31:0] tar_temp[200:0];
wire [31:0] nmr [14:0];
wire [31:0] nmr_temp[14:0] [10:0];
wire [31:0] dnr [14:0];
wire [31:0] scr [14:0];
reg [31:0] a [14:0] [10:0];
//wire [31:0] b [3:0] [9:0];
wire [31:0] c [14:0] [9:0];

 
 assign nmr_temp[0][0]=32'h00000000;
 assign nmr_temp[1][0]=32'h00000000;
 assign nmr_temp[2][0]=32'h00000000;
 assign nmr_temp[3][0]=32'h00000000;
assign nmr_temp[4][0]=32'h00000000;
assign nmr_temp[5][0]=32'h00000000;
assign nmr_temp[6][0]=32'h00000000;
assign nmr_temp[7][0]=32'h00000000;
assign nmr_temp[8][0]=32'h00000000;
assign nmr_temp[9][0]=32'h00000000;
assign nmr_temp[10][0]=32'h00000000;
assign nmr_temp[11][0]=32'h00000000;
assign nmr_temp[12][0]=32'h00000000;
assign nmr_temp[13][0]=32'h00000000;
assign nmr_temp[14][0]=32'h00000000;
assign en = rst? 1'b0 : 1'b1;


always @(posedge clk)
begin
  rst_1 <= rst;
  // if (rst)
    // en <= 1'b0;
  // else
  // begin
    // en <= 1'b1;
  // end
  if (en)
  // always @ (posedge en)
  begin
//target i-vectors
 a[0][0]=32'b10111111101010101010010100010101;
a[0][1]=32'b11000000000000111111000000110100;
a[0][2]=32'b00111111111010010010101000111010;
a[0][3]=32'b10111111100110111010111011010001;
a[0][4]=32'b01000000000101001110010011100101;
a[0][5]=32'b01000000001001011010001000010001;
a[0][6]=32'b10111110100001001111101010010111;
a[0][7]=32'b00111111101101111100001001111000;
a[0][8]=32'b11000000011100001100010010001001;
a[0][9]=32'b10111111111101000110000011000000;
a[0][10]=32'b01000000001001011010001000010001;
a[1][0]=32'b01000001000010011001010101101110;
a[1][1]=32'b01000000000001010110101011011111;
a[1][2]=32'b01000000001101111010010111110001;
a[1][3]=32'b00111110100010111011111100101011;
a[1][4]=32'b10111110011000101000011010100001;
a[1][5]=32'b11000000000010011011010101010011;
a[1][6]=32'b10111111101100010110001000000010;
a[1][7]=32'b01000000000001101111001100111111;
a[1][8]=32'b00111110001001011100100000111100;
a[1][9]=32'b00111111110000011100101101100110;
a[1][10]=32'b01000000001001011010001000010001;
a[2][0]=32'b01000000111101101110111011011100;
a[2][1]=32'b00111111100011100011100001111010;
a[2][2]=32'b01000000100000011010111100110101;
a[2][3]=32'b00111111001001010000011011000101;
a[2][4]=32'b00111111101010111101100001010011;
a[2][5]=32'b11000000001011000010101111011011;
a[2][6]=32'b10111111100001101100110010101111;
a[2][7]=32'b01000000000010011100001001111101;
a[2][8]=32'b00111110001101111101101000110111;
a[2][9]=32'b11000000001001010001010100000101;
a[2][10]=32'b01000000001001011010001000010001;
a[3][0]=32'b01000000001001111001011011000111;
a[3][1]=32'b00111110100000000010001000011011;
a[3][2]=32'b00111110110011010111011100110111;
a[3][3]=32'b00111110011010110111001110010111;
a[3][4]=32'b00111110110111100110110001011001;
a[3][5]=32'b10111111010111110111100111101101;
a[3][6]=32'b00111111011100001110001010101110;
a[3][7]=32'b10111110111101011000100101011111;
a[3][8]=32'b11000000000010110111011100011110;
a[3][9]=32'b10111111111111101111000010011011;
a[3][10]=32'b01000000001001011010001000010001;
a[4][0]=32'b01000000000011011110111001110010;
a[4][1]=32'b11000000110000010010110000000110;
a[4][2]=32'b10111111010000111010101001100111;
a[4][3]=32'b00111111100010010000000101010010;
a[4][4]=32'b00111110111010001111111010010111;
a[4][5]=32'b11000000000010010101000010011101;
a[4][6]=32'b11000000000010100111000001101011;
a[4][7]=32'b10111101010111101110011011000001;
a[4][8]=32'b00111111110100111101100111010110;
a[4][9]=32'b00111111100100001011111010001000;
a[4][10]=32'b01000000001001011010001000010001;
a[5][0]=32'b01000000001110001000100011011110;
a[5][1]=32'b10111110010000110111111101111011;
a[5][2]=32'b10111110001110001011100100001011;
a[5][3]=32'b11000000100110101010101001001000;
a[5][4]=32'b11000000001100110010011100110111;
a[5][5]=32'b00111111001001100101001011011011;
a[5][6]=32'b01000000001010011111110000101010;
a[5][7]=32'b10111111100101101011011111110001;
a[5][8]=32'b00111111111101010001011100000100;
a[5][9]=32'b11000000000100000100011001110000;
a[5][10]=32'b01000000001001011010001000010001;
a[6][0]=32'b11000000010110010011100001101110;
a[6][1]=32'b10111111000001001010111001011011;
a[6][2]=32'b00111111100111111100010000101101;
a[6][3]=32'b10111111011100110011101101001000;
a[6][4]=32'b01000000010000000110001111010000;
a[6][5]=32'b01000000011110110100010101111011;
a[6][6]=32'b00111111010110000110011110001000;
a[6][7]=32'b10111110110100100001010111010001;
a[6][8]=32'b10111111110111001001100000101010;
a[6][9]=32'b00111110100000100010010100011010;
a[6][10]=32'b01000000001001011010001000010001;
a[7][0]=32'b10111111001010001111110000101110;
a[7][1]=32'b11000000000110101011110111100111;
a[7][2]=32'b00111111101001110000011110110100;
a[7][3]=32'b01000000000001000110110010000001;
a[7][4]=32'b00111111110000001001101110100010;
a[7][5]=32'b01000000011001011101110111100110;
a[7][6]=32'b01000000001111011010011101111110;
a[7][7]=32'b10111101010110000011001011000100;
a[7][8]=32'b10111101000110000101111011011101;
a[7][9]=32'b00111111111000010000000100001101;
a[7][10]=32'b01000000001001011010001000010001;
a[8][0]=32'b00111111001011101001101011111100;
a[8][1]=32'b11000000100010010110100010101001;
a[8][2]=32'b00111101101000011100000110000101;
a[8][3]=32'b00111111011110001110110101100110;
a[8][4]=32'b00111111000101001100010001011101;
a[8][5]=32'b01000000000000101000001110110101;
a[8][6]=32'b00111011111000110010011100110001;
a[8][7]=32'b00111111000001110000001111100110;
a[8][8]=32'b00111101100010100011100000001010;
a[8][9]=32'b00111110111110001111011001011011;
a[8][10]=32'b01000000001001011010001000010001;
a[9][0]=32'b01000000000101110011010100001100;
a[9][1]=32'b01000000100110010111101000101111;
a[9][2]=32'b01000000000110110110111010110000;
a[9][3]=32'b00111111110001011100011111010101;
a[9][4]=32'b10111101110100101011001100011100;
a[9][5]=32'b01000000000110100100010111101101;
a[9][6]=32'b10111111101111001011010001111101;
a[9][7]=32'b01000000000011110000011010111101;
a[9][8]=32'b10111111110100001110010010110101;
a[9][9]=32'b11000000111011001110101010010100;
a[9][10]=32'b01000000001001011010001000010001;
a[10][0]=32'b11000000100111111101000110100100;
a[10][1]=32'b00111111101110110010000001110111;
a[10][2]=32'b00111111110000111100000011111110;
a[10][3]=32'b10111111010101000000100101111111;
a[10][4]=32'b10111111101100000000010010001101;
a[10][5]=32'b00111111100000110101111111000111;
a[10][6]=32'b01000000011011000010110101011101;
a[10][7]=32'b00111111111101011101001111010101;
a[10][8]=32'b10111111100010001010100001011101;
a[10][9]=32'b11000000000011110011101011001000;
a[10][10]=32'b01000000001001011010001000010001;
a[11][0]=32'b01000001000111011100110111111101;
a[11][1]=32'b11000000101010100001110000011010;
a[11][2]=32'b11000000000101101000000101111111;
a[11][3]=32'b10111111011101001011101001010010;
a[11][4]=32'b11000000001101111001000010010110;
a[11][5]=32'b01000000001110101011101011100000;
a[11][6]=32'b01000000000110111010011101100110;
a[11][7]=32'b10111111100000000000010011010100;
a[11][8]=32'b01000000100001000111111000110001;
a[11][9]=32'b10111111111011101010001000110100;
a[11][10]=32'b01000000001001011010001000010001;
a[12][0]=32'b00111111111101011001100010011100;
a[12][1]=32'b10111111000000111101100001001110;
a[12][2]=32'b01000000011001101101011000011001;
a[12][3]=32'b01000000010100100010000110111110;
a[12][4]=32'b10111111111010001101100111111100;
a[12][5]=32'b01000000001001011100010110010010;
a[12][6]=32'b01000000000010100000111111101010;
a[12][7]=32'b10111111001100101000001101110010;
a[12][8]=32'b01000000100100110100101010111011;
a[12][9]=32'b00111111101011111000111011010110;
a[12][10]=32'b01000000001001011010001000010001;
a[13][0]=32'b10111111111110100101010000001011;
a[13][1]=32'b10111110101001001100100111101100;
a[13][2]=32'b00111111101011000110100001111101;
a[13][3]=32'b10111111100000100111100101001110;
a[13][4]=32'b01000000000000001100001001011000;
a[13][5]=32'b01000000011000010110111000101011;
a[13][6]=32'b01000000000011010111000111011001;
a[13][7]=32'b00111111010101000010001010110100;
a[13][8]=32'b10111111110010010111101000110110;
a[13][9]=32'b10111111100001001101011101110001;
a[13][10]=32'b01000000001001011010001000010001;
a[14][0]=32'b11000000001101100111001011001000;
a[14][1]=32'b00111110101000001110001010111011;
a[14][2]=32'b01000000001010110011010111011111;
a[14][3]=32'b00111110110100100100110011001000;
a[14][4]=32'b00111111011110110010001011111010;
a[14][5]=32'b00111111111111011010010011101010;
a[14][6]=32'b00111111011010011100110010100001;
a[14][7]=32'b01000000001011000101111101101011;
a[14][8]=32'b11000000001010011110110000011110;
a[14][9]=32'b11000000000001100001100100001010;
a[14][10]=32'b01000000001001011010001000010001;



//selecting the test vector  
case (sel)
  
  4'd0: begin
     in[0]=32'b01000000000010001010001111010111;
 in[1]=32'b00111111011100010101010001101010;
 in[2]=32'b00111111001101001111101000100010;
 in[3]=32'b00111111011000001110101110100001;
 in[4]=32'b10111110010110000100000100111011;
 in[5]=32'b00111110101001101011000111011010;
 in[6]=32'b00111110100111110000000010001100;
 in[7]=32'b10111111000101101001010101111010;
 in[8]=32'b10111111110000100010011011000100;
 in[9]=32'b10111111111011011010001011100010;
 in[10]=32'b00111110100111110000000010001100;



end

4'd1:begin
   in[0]=32'b01000000111000111111000110001111;
 in[1]=32'b11000000100011000001011111100110;
 in[2]=32'b00111110110011100111001001100111;
 in[3]=32'b01000000000101000001011010011100;
 in[4]=32'b10111111000011001010101110011100;
 in[5]=32'b10111111111010000110001101011111;
 in[6]=32'b01000000000011010101101011101011;
 in[7]=32'b10111101010110110100010101111100;
 in[8]=32'b11000000001100010011101011111011;
 in[9]=32'b11000000100010101100010101000010;
  in[10]=32'b00111110100111110000000010001100;
end

4'd2:begin
 in[0]=32'b11000000001011011000101111110000;
 in[1]=32'b10111111101110011010001000110010;
 in[2]=32'b01000000000110101000110010100110;
 in[3]=32'b00111111000000011011001101111010;
 in[4]=32'b00111110000110000010101100010011;
 in[5]=32'b01000000011010000001000000110011;
 in[6]=32'b00111111110010101100111011101111;
 in[7]=32'b00111111111110111001110010011110;
 in[8]=32'b11000000001010100001100001111110;
 in[9]=32'b10111111101101001110000111100001;
  in[10]=32'b00111110100111110000000010001100;


end

4'd3:begin
    in[0]=32'b10111111100111001001000110110101;
 in[1]=32'b11000000001010000100001001011111;
 in[2]=32'b00111111000011000111011000011011;
 in[3]=32'b00111111111001100010011011110001;
 in[4]=32'b00111111001011110011101000000100;
 in[5]=32'b01000000010011011010010000001101;
 in[6]=32'b00111111110001110100110110110011;
 in[7]=32'b10111111011100111100101001111011;
 in[8]=32'b10111111011001000111010111100011;
 in[9]=32'b00111111100110111101100111001101;
  in[10]=32'b00111110100111110000000010001100;
 end

endcase

end
end
// end


genvar i,j;
generate
for (j=0; j<15; j=j+1)
  begin : first
  for (i=0; i<10; i=i+1)
  begin : second
    //multiplier m1(in1[i],in[i],in[i]);
    //adder a1(test[j][i+1],test[j][i],in1[i]);
    //multiplier m2(b[j][i],a[j][i],a[j][i]);
    //adder a2(tar[j][i+1],tar[j][i],b[j][i]);
    multiplier m3(c[j][i],a[j][i],in[i]);
    adder a3(nmr_temp[j][i+1],nmr_temp[j][i],c[j][i]);
  end
  multiplier m4(nmr[j],nmr_temp[j][10],nmr_temp[j][10]);
  multiplier m5(dnr[j],a[j][10],in[10]);
  divider d1(rst_1,clk,nmr[j],dnr[j],scr[j]);
  end
  
endgenerate

assign out0  = rst ? 32'b0 : scr[0] ; 
assign out1  = rst ? 32'b0 : scr[1] ; 
assign out2  = rst ? 32'b0 : scr[2] ; 
assign out3  = rst ? 32'b0 : scr[3] ; 
assign out4  = rst ? 32'b0 : scr[4] ; 
assign out5  = rst ? 32'b0 : scr[5] ; 
assign out6  = rst ? 32'b0 : scr[6] ; 
assign out7  = rst ? 32'b0 : scr[7] ; 
assign out8  = rst ? 32'b0 : scr[8] ; 
assign out9  = rst ? 32'b0 : scr[9] ; 
assign out10 = rst ? 32'b0 : scr[10]; 
assign out11 = rst ? 32'b0 : scr[11]; 
assign out12 = rst ? 32'b0 : scr[12]; 
assign out13 = rst ? 32'b0 : scr[13]; 
assign out14 = rst ? 32'b0 : scr[14]; 
endmodule
 
Last edited:

Your problem has more to do with poor architecture, you've implemented 100s of constants in FFs. Then you use those 100s of FF constants in 150 multiplier instances (all in parallel). Given the way you've coded this you are trying to implement something with 150 multiply accumulates in a single clock cycle. Are you really sure this is what you want to do?

If you really want them in parallel then don't put the constants in a FF make them all assigns then the synthesis tool can optimize the heck out of the multipliers and adders if it's possible to do so. Of course then you'll still have problems with exceeding the total LUTs due to the huge gate level multipliers you probably implemented in the multiplier module. Once again do you really need to produce all the multiplies in a single clock cycle?


Besides that, a general comment on your code quality. You've managed to use nearly every bad coding practice in a single file:
* pre-2001 ports,
* poor formating
* non-descriptive signal naming
* possible conflicting assign statements (i.e. multiple drivers) for the nmr_temp signal (though can't be sure about that due to missing addr code, but I doubt you want nmr_temp to stay 0 forever)
* using blocking assignments in a edge triggered (clocked) always block
* using positional association, instead of named association for an instantiated module.
 
I changed blocking statement to non-blocking ? how blocking statement effect my design?
 

I changed blocking statement to non-blocking ? how blocking statement effect my design?

In this instance they don't affect anything, but as a general rule using blocking statements in a clock always block (that represents parallel logic, i.e. Flip-flops) is a bad idea as blocking statements represent combinational logic as opposed to parallel logic, i.e. blocking assignments block all further assignments until the blocking statement evaluation is completed.
 

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