help for vhdl error in qu(at)rtus II Analysis & Synthesi

help needed for vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity recoredor is
port (
A,B,C,D: in std_logic;

S0,S1,S2,S3,S4,S5,S6,S7ut std_logic);
end recoredor;

architecture ejemplo of recoredor is
begin
S0<=((not(A) and not(B) and not(C) and not(D)) or (A and B and C and D))
S1<=((not(A) and not(B) and not(C) and D) or (A and B and C and not (D)))
S2<=((not(A) and not(B) and C and not(D)) or (A and B and not(C) and D))
S3<=((A and B and not(C) and not(D)) or (not(A) and not(B) and C and D))
S4<=((not(A) and B and not(C) and not(D)) or (A and not(B) and C and D))
S5<=((A and not(B) and C and not(D)) or (not(A) and B and not(C) and D))
S6<=((A and not(B) and not(C) and D) or (not(A) and B and C and not(D)))
S7<=((A and not(B) and not(C) and not(D)) or (not(A) and B and C and D))
end ejemplo;


geting

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Sep 21 02:50:15 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off practica -c practica
Error (10500): VHDL syntax error at practica.vhd(14) near text "S1"; expecting ";"
Info: Found 0 design units, including 0 entities, in source file practica.vhd
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 186 megabytes
Error: Processing ended: Mon Sep 21 02:50:18 2009
Error: Elapsed time: 00:00:03
Error: Total CPU time (on all processors): 00:00:03
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings

help needed for vhdl

VHDL syntax error ... near text "S1"; expecting ";"

Click to expand...

Yes. VHDL expressions are expected to have a delimiting ";". Q.uartus is only showing the first serious error in this case, actually it's present 8 times.