library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package matrix_pkg is
type matrix_D2 is array (integer range <>, integer range <>) of signed(31 downto 0);
constant a_in: matrix_D2(1 to 1,1 to 19) := (1=>(
x"00000033", x"0000004b", x"0000004b", x"0000004b", x"ffffffd7",
x"ffffff6a", x"0000004b", x"0000004b", x"00000021", x"ffffff6d",
x"0000004b", x"0000004b", x"00000041", x"ffffff6a", x"ffffff6a",
x"ffffff6a", x"ffffffe6", x"0000004b", x"00000041" ));
end ;
------------------------------------------------------------
LIBRARY IEEE;
USE work.matrix_pkg.all ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY test01 IS
GENERIC (F : integer:=8;
E : integer:=1);
PORT (
featurs_in: IN matrix_D2(1 to F, 1 to E); -- 8x1 matrix ;
ready_class : out std_logic := '0' ;
class_out: OUT std_logic_vector(1 downto 0)
) ;
END test01;
ARCHITECTURE rtl OF test01 IS
COMPONENT test02 IS
GENERIC (M : integer:=3;
N : integer:=2;
K : integer:=1;
L : integer:=1);
PORT (
a_in: IN matrix_D2(1 to M, 1 to N); -- MxN matrix ; -- 19x8
b_in: IN matrix_D2(1 to N, 1 to K); -- NxK matrix ; -- 8x1
c_in: IN matrix_D2(1 to L, 1 to M); -- LxM matrix ; -- 1x19
clk: IN STD_LOGIC;
reset: IN STD_LOGIC;
ready : out std_logic := '1' ;
d_out: OUT matrix_D2(1 to L, 1 to K)-- LxK matrix ;
) ;
END COMPONENT;
component ... is
.
.
end component ;
component ... is
.
.
end component ;
component ... is
.
.
end component ;
SIGNAL ready_1,ready_2,ready_3 : std_logic ;
SIGNAL out_1,out_2,out_3 : matrix_D2(1 to 1, 1 to 1);
..
..
..
test02_1 : test02
generic map (19,8,1,1)
port map (bbb_in, featurs_in, a_in, clk, reset, ready_1, out_1);
-- bbb_in it's also like a_in , it's matrix but it's too long to used it in herem;
..
..
..
..
..
end rtl ;