Help for verilog uart tx?

[tumee]

Hello every one.
I have same problem about below tx code.
Here is a verilog uart transmit code.
Here I can send only one character to computer via rs232. In below code can send only 'X' char.
I need to send word by word to computer.
Please help.

module TX ( pin_clk, // external 12M global clock pin_key, // KEY0, KEY1 key input pin_txd // Serial UART transmitter ); /********************** Port type definition *******************/ input pin_clk; input [1:0] pin_key; output pin_txd; /********************** Internal variable definitions **********/ reg [10:0] tx_baud; // Send Baud Rate Timer reg [9:0] tx_buff; // Transmit buffer reg [10:0] send_data; wire rst; // Reset /***************************************************************/ assign rst = ~pin_key[0]; // Global reset signal (F1 key) /* Transmit baud rate */ always @ (posedge pin_clk or posedge rst) if (rst ==1'b1) tx_baud <= 11'h000; else if (tx_baud == 11'h4e1) tx_baud <= 11'h000; else tx_baud <= tx_baud + 1'b1; /************** Shift register transmitted once ****************/ always @(posedge pin_clk or posedge rst) if (rst ==1'b1) tx_buff <= (send_data << 2) | 10'b0000000001; else if (tx_baud == 11'h4e1) begin tx_buff[0] <= tx_buff[1]; tx_buff[1] <= tx_buff[2]; tx_buff[2] <= tx_buff[3]; tx_buff[3] <= tx_buff[4]; tx_buff[4] <= tx_buff[5]; tx_buff[5] <= tx_buff[6]; tx_buff[6] <= tx_buff[7]; tx_buff[7] <= tx_buff[8]; tx_buff[8] <= tx_buff[9]; tx_buff[9] <= 1'b1; end assign pin_txd = tx_buff[0]; always @ (posedge pin_clk or posedge rst) begin send_data <= "X"; end /****************** End module *******************/ endmodule

 

[wade_hassler]

1. Add an output from the module that says Busy/Not_busy
2. Write a module that

Instantiates Xmitter

Resets Xmitter
Using an FSM :

After reset, go to state_0
State_0: if Xmitter not-busy:
Send_first_value_to_Xmitter
Wait_while_Busy
go to state_1
State_1: if Xmitter not_busy
Send_second_value_to_Xmitter
Wait_while_Busy
go to state_2
​

.. and repeat the above until you run out of data
​

Also, delete the lines
always @ (posedge pin_clk or posedge rst)
begin
send_data <= "X";
end
...from the module code