help for adding coregen single port ram to a vhdl of a custom IP

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aminbahrami

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Hi all

in ise we use CoreGen to add single port rom and specify a coe file as initial data to the created single port rom then we portmap it and use it.

I want to integrate microblaze and VHDL together in xps.

I created a project in xps using bsb.

then I created a custom peripheral and added my VHDL code using this peripheral(by instantiating my code instance to user logic).

now I want use from a single port rom in my VHDL because I have so many initial data for process.

can anyone help me plz?
thanx
 

Thanx my dear friend
It was so useful for me
 

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