ahgu
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I need to read data from several camera and dump them into either high speed USB or Giga-E.
Total Camera bandwidth 140Mb/s
Cameras--FPGA---RAM(at least 16Mb)
MCU with USB+GIGAE.
One way is to use FPGA for everything including USB and GIGAE, but I have to write too much verilog code.
I want to use the MCU that already has USB/GIGE feature, so FPGA put the data into RAM and MCU send it out through USB/GIGE. The problem is how does the MCU interface with the RAM? What is the optimal way?
Seems it must go through FPGA so the read/write does not interfere. MCU has 16bit DDR1,2 interface logic. The RAM does not have dual interface like FIFO. right?
Thank you
Total Camera bandwidth 140Mb/s
Cameras--FPGA---RAM(at least 16Mb)
MCU with USB+GIGAE.
One way is to use FPGA for everything including USB and GIGAE, but I have to write too much verilog code.
I want to use the MCU that already has USB/GIGE feature, so FPGA put the data into RAM and MCU send it out through USB/GIGE. The problem is how does the MCU interface with the RAM? What is the optimal way?
Seems it must go through FPGA so the read/write does not interfere. MCU has 16bit DDR1,2 interface logic. The RAM does not have dual interface like FIFO. right?
Thank you
