Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Help: asynchronous FIFO design!

Status
Not open for further replies.

Alvinnju

Newbie level 6
Joined
Mar 31, 2005
Messages
13
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,374
asynchronous fifo design

The read comarator compares the value of the read and write flags associated with the second-next read-pointer position.The FIFO empty is set if the flags have the same value.similarity,the FIFO full is set if the fread and the second-next write-pointer position have the same value.

But if do like this,it's impossible to read the last word in the momery.how to deal...

Thanks!
 

nittinsharma80

Member level 5
Joined
Apr 11, 2005
Messages
93
Helped
11
Reputation
22
Reaction score
2
Trophy points
1,288
Location
INDIA
Activity points
2,337
asynchronous fifo

Hi
just go through basics of the FIFOs.
find attached one doc for that
i hope it helps
 

bibo1978

Full Member level 4
Joined
May 1, 2004
Messages
210
Helped
12
Reputation
24
Reaction score
6
Trophy points
1,298
Activity points
2,548
fifo design

this can be done with two schemes,
A-adding an extra bit on the counter used as a flag, for example if you have a 16 word FIFO, then you use a 5 bit counter rather than 4-bit counter, this way comparing this extra bit will flag you if you are going to full or empty.
B-to use a direction flag according to the position of the counter in a four quadrant, i.e. according to the last two bits of the counter if the read lags the write then this flag may be used to indicate that you are going to be empty and if the write lags the read then you r going to be full, this direction flag simply informs when an equality condition happens wether if you are full or empty.
you can use an asynchronous set/reset FF to do this flag, however if you want to stick with the reuse methodology manual rules you can use a flancter.

The second technique is more appealing to me rather in high speed FIFO.

Note that FIFO design includes other technical issues you have to take care of, llike metastability and glitches occurs during comparison of counters.
metastability can be solved using the ordinary two cascaded FF metastability filters
glitches can be solved using gray code counter, and with low delay on nets you can improve the uncertainity time in your design, if you used a gray code counter you will not have to worry about glitches "non will occur".
gray counter can be done using a binary counter followed by binary-to-gray conversion and registeration, the binary counter can address the FIFO while the encoded gray code can be used for comparison this technique will decrease you fanout but increase the area, suitable for high speed application.
 

power-twq

Full Member level 6
Joined
Jun 10, 2005
Messages
373
Helped
8
Reputation
16
Reaction score
3
Trophy points
1,298
Activity points
4,550
async fifo code

The last word canbe read after a few clock cycles later.

no problem.



Alvinnju said:
The read comarator compares the value of the read and write flags associated with the second-next read-pointer position.The FIFO empty is set if the flags have the same value.similarity,the FIFO full is set if the fread and the second-next write-pointer position have the same value.

But if do like this,it's impossible to read the last word in the momery.how to deal...

Thanks!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top