Help about my first VHDL code

[kkdelabaca]

hello

Somebody can help me to translate this schematic to one VHDL code?
I do not understand how connect the internal nodes.

THANKS !!

**broken link removed**

/***************************************************************/
/***************************************************************/
/******************** CODE FOR MULTIPLEXOR *********************/
/***************************************************************/

library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------

entity Mux is
port( I3: in std_logic_vector(2 downto 0);
I2: in std_logic_vector(2 downto 0);
I1: in std_logic_vector(2 downto 0);
I0: in std_logic_vector(2 downto 0);
S: in std_logic_vector(1 downto 0);
O: out std_logic_vector(2 downto 0)
);
end Mux;

-------------------------------------------------

architecture behv1 of Mux is
begin
process(I3,I2,I1,I0,S)
begin

-- use case statement
case S is
when "00" => O <= I0;
when "01" => O <= I1;
when "10" => O <= I2;
when "11" => O <= I3;
when others => O <= "ZZZ";
end case;

end process;
end behv1;

/***************************************************************/
/***************************************************************/
/***********************CODE FOR COUNTER **********************/
/***************************************************************/

library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

----------------------------------------------------

entity counter is

generic(n: natural :=2);
port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end counter;

----------------------------------------------------

architecture behv of counter is

signal Pre_Q: std_logic_vector(n-1 downto 0);

begin

-- behavior describe the counter

process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;

-- concurrent assignment statement
Q <= Pre_Q;

end behv;

 

[FvM]

I see that are apparently using Altera MaxPlus II or Quartus software. At least the latter can generate VHDL code from the schematic. A simple way to get a reference dessign.

Apart from this option, talking about systematic VHDL design, you are missing the design top level. Another entity, that has the intended external signals as ports and instantiates the two components, you are showing in your post. You have to know the basic syntax for component instantiation of course. Quartus VHDL editor has a nice template tool, that can show you all basic syntax elements while you're writing the VHDL code.

However, the components are not exactly fitting the schematic. The binary counter must have three bits rather than two (can be changed in a generic port) and you only need one bit of your three bit MUX.

You may want to consult a VHDL text book, too. The Synopsys VHDL compiler manual is also a good reference to my opinion

 

[ombadei]

Hi.. On the manual that you have posted, what does the Synopsis VHDL compiler do?

 

[aapatel374]

u can use stuctural method for it.then using component u can connect all internal wires.refer pedroni(book) for it.

 

[FvM]

On the manual that you have posted, what does the Synopsis VHDL compiler do?

It's a VHDL compiler similar to Q.uartus integrated analysis. As said, I suggested the manual as a VHDL reference, there's little Synopsis specific stuff in it.