I can tell you what I used in my circuit.
Basically I used one schmitt trigger, After that two capacitors (one to vdd & another to gnd). This will be equivalent to RC low pass, (R I am refering to that of the MOS). After that you can connect another schmitt trigger.
So its basically
signal-->schmitt trigger->CAP to vdd & gnd->2nd Schmitt trigger.
So to design,choose the capacitor & then size the First schmitt trigger mos's W/L so to suppress the 50ns Pulse.
This 50ns pulse suppression means that if I give 50ns Pulse (whose logic high time is 50ns) then it should not be reflected to the output to the core side.(Not even glitch).
But there is some ambiguity, The I2C specs does not specify whether it is single pulse or multiple stream of pulses. Beacause in the later case, after some time, the circuit will start responding to the stream of pulses as the internal points do not have time to discharge to steady state value.