HELP a VHDL Arithmetic and Logic Unit (ALU)

[jakilax]

Hey guys, I was wondering if someone could give me a hand with designing a specific ALU.

Here is what I would like to implement:
- sequentlial unit with 2 registers (e.g. Acc and Data_Reg)
- immediate Read and Write Access to Acc
- 4 funtion bits (S01 - S03) to select an OpCode (see table below)
- ALU should flag for Acc = 0 (CPZ), for overflow (OVR) and for Acc = Data_Reg (AED)


S01 S02 S03 S04
0......0......0......0......RES RESET Acc to 00000000 (Arith)
0......0......0......1......INC Acc = Acc + 1 (Arith)
0......0......1......0......ADD Acc = Acc + Data_Reg (Arith)
0......0......1......1......SUB Acc = Acc - Data_Reg (Arith)
0......1......0......0......MUL Acc = Acc x Data_Reg (Arith)
0......1......0......1......SHL Acc = Acc shifted left (up) by Data_Reg bits
0......1......1......0......SHR Acc = Acc shifted right (down) by Data_Reg bits
0......1......1......1......AND Acc <= Acc NAND Data_Reg (Logic)
1......0......0......0......XOR Acc <= Acc EXOR Data_Reg (Logic)
1......0......0......1......SET SET Acc to 11111111 (Arith)
1......0......1......0......LDA Load Acc from Data RAM (Cntrl)
1......0......1......1......LDD Load Data_Reg from Data RAM (Cntrl)
1......1......0......0......STA Store Acc to Data RAM (Cntrl)
1......1......0......1......STE Store External Data to Data RAM (Cntrl)
1......1......1......0......INZ Increment PC if ZFL = '1' (Cntrl)
1......1......1......1......JMP Jump to P(x)C if ZFL = '1' (Cntrl)


any help would be highly appreciated xx

 

[TrickyDicky]

what have you done so far - and what specific problems are you having?>

 

[jakilax]

thanks for comming back to me and sorry for being so imprecise!

here is what I've done so far (I basically strugle with everything which is not implemented):


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity simple_alu is
port( Clk : in std_logic; --clock signal
Acc, Data_Reg : in std_logic_vector (7 downto 0); --input operands
Op : in std_logic_vector(3 downto 0); --Operation to be performed
R : out std_logic_vector(7 downto 0) --output of ALU
);
end simple_alu;

architecture Behavioral of simple_alu is

--temporary signal declaration.
signal Reg1,Reg2,Reg3 : std_logic_vector(7 downto 0) := (others => '0');

begin

Reg1 <= Acc;
Reg2 <= Data_Reg;
R <= Reg3;

process(Clk)
begin

if(rising_edge(Clk)) then --Do the calculation at the positive edge of clock cycle.
case Op is
when "0000" => Reg3 <= '00000000' --0 RES RESET Acc to 00000000 (Arith)
when "0001" => Reg3 <= --1 INC Acc = Acc + 1 (Arith)
when "0010" => Reg3 <= Reg1 + Reg2; --2 ADD Acc = Acc + Data_Reg (Arith)
when "0011" => Reg3 <= Reg1 - Reg2; --3 SUB Acc = Acc - Data_Reg (Arith)
when "0100" => Reg3 <= --4 MUL Acc = Acc x Data_Reg (Arith)
when "0101" => Reg3 <= --5 SHL Acc = Acc shifted left (up) by Data_Reg bits
when "0110" => Reg3 <= --6 SHR Acc = Acc shifted right (down) by Data_Reg bits
when "0111" => Reg3 <= Reg1 nand Reg2; --7 Acc <= Acc NAND Data_Reg (Logic)
when "1000" => Reg3 <= Reg1 xor Reg2; --8 Acc <= Acc EXOR Data_Reg (Logic)
when "1001" => Reg3 <= --9 SET Acc to 11111111 (Arith)
when "1010" => Reg3 <= --A Load Acc from Data RAM (Cntrl)
when "1011" => Reg3 <= --B Load Data_Reg from Data RAM (Cntrl)
when "1100" => Reg3 <= --C Store Acc to Data RAM (Cntrl)
when "1101" => Reg3 <= --D Store External Data to Data RAM (Cntrl)
when "1110" => Reg3 <= --E Increment PC if ZFL = '1' (Cntrl)
when "1111" => Reg3 <= --F Jump to P(x)C if ZFL = '1' (Cntrl)
when others => Reg3 <= (others => '0');
end case;
end if;

end process;

end Behavioral;

 

[TrickyDicky]

what specific question do you have?

 

[jakilax]

what specific question do you have?

e.g.

- how do I implement an immediate Read and Write Access to Acc?
- how to flag the ALU for Acc = 0 (CPZ), for overflow (OVR) and for Acc = Data_Reg (AED)

 

[TrickyDicky]

1. you know what the opcode is, so you just set the "R" output to whatever value you want
2. You probably need an extra overflow output, that may interrupt the processor. And the = is just an "=" function.

 

[jakilax]

1. you know what the opcode is, so you just set the "R" output to whatever value you want
2. You probably need an extra overflow output, that may interrupt the processor. And the = is just an "=" function.

thanks for your quick response! it's very much appreciated.
unfortunatelly, I honestly don't understand at all how to "realize" your hints as my knowledge in VHDL is super limited:-(

could you do me a favour please and give me a code example for both?!

 

[TrickyDicky]

its not clear what you're doing. Are your questions related to external access to the ALU, or from inside?

 

[jakilax]

its not clear what you're doing. Are your questions related to external access to the ALU, or from inside?

external access

 

[TrickyDicky]

Then the question you are asking doesnt relate to this block, as ACC is an input - to write to ACC you just connect it externally to something. And you cannot read from ACC, unless you just wire it straight back to the output R.

 

[jakilax]

Then the question you are asking doesnt relate to this block, as ACC is an input - to write to ACC you just connect it externally to something. And you cannot read from ACC, unless you just wire it straight back to the output R.

haha, why are you asking then if it's external access to the ALU or from the inside? anyways.
all the code I posted is probably nonsense and might be not useful at all (that's why I didn't implement it in the first post - in order to avoid confusion). Also, in the first post I described what I would like to do but apparently not able to do as I'm completely new to FPGAs and VHDL. I don't want anyone to solve this "task" but I wouldn't mind if someone actually would help ;-)

 

[TrickyDicky]

I would suggest forgetting the VHDL for now, and think about the actual circuit. Can you draw the circuit for the ALU? VHDL is a description language, and you cannot write code if you dont understand the circuit. I suggest drawing out first what you're trying to acheive.

 

[jakilax]

I would suggest forgetting the VHDL for now, and think about the actual circuit. Can you draw the circuit for the ALU? VHDL is a description language, and you cannot write code if you dont understand the circuit. I suggest drawing out first what you're trying to acheive.

ok, I've got it on paper now. not sure how that could possibly help me. anyways.
Cheers and bye!

 

[TrickyDicky]

If you have drawn the circuit on paper, then you should now understand the logic elements required to build the circuit. Now it will be easy to write the VHDL as all of them have basic templates you should follow.

 

[jakilax]

nope, unfortunately not

 

[TrickyDicky]

Well what you should have is 16-1 mux with each input connected to another small bit of logic.

WHy not post your diagram.