It's nice to first generate higher than 1.5x voltage, then place a MOS in series at output, use feedback to control gate of MOS.
You can either use PMOS (just like a LDO) or a NMOS (HDO) for the regulation.
I prefer HDO approach because even at the frequency beyond your close loop bandwidth, Rout still remains low (assume IL is significant) while LDO Rout drastically increases.
The catch is how to make HDO gate drive voltage free of ripple (since you might have to tap it from the high voltage available) -- I will leave it to your innovation. :twisted: :roll:
If output voltage ripple is not concern, you might easily get away by making the switch MOS into variable resistor through output feedback. That's exactly what TI did in their parts. :!: