ciacco85
Newbie level 3
That's my first thread in this board, so hi all 
I'm realizing an HDL synthesizable model with simulink. I'm facing problem with blocks that needs an output sample time higher than input like
- pilot insertion: from a continuous stream of data i should insert samples from a sequence (ex: in 2k-mode, every 1512 data input i should insert 1704-1512=192 pilot and than center-zero-pad to reach 2048 without loosing any data input sample
- cyclic prefix: when all these 2048 are modulated through "HLD streaming FFT", modified to computed an iFFT, i have to add the prefix.
My problem is that i can't use frame based block (like what is done in simulink ofdm demos) because they are not HDL synthetizable.
Maybe there are different way other than change the sample time of block (like using temp-fifo/RAM) but i can't figure it out and the fun thing is that doing something like that in VHDL is so easy
NB: a friend of mine has the same problem in Reed-Solomon code where from 188 byte-in he needs 204 byte-out! Please help us!!
I'm realizing an HDL synthesizable model with simulink. I'm facing problem with blocks that needs an output sample time higher than input like
- pilot insertion: from a continuous stream of data i should insert samples from a sequence (ex: in 2k-mode, every 1512 data input i should insert 1704-1512=192 pilot and than center-zero-pad to reach 2048 without loosing any data input sample
- cyclic prefix: when all these 2048 are modulated through "HLD streaming FFT", modified to computed an iFFT, i have to add the prefix.
My problem is that i can't use frame based block (like what is done in simulink ofdm demos) because they are not HDL synthetizable.
Maybe there are different way other than change the sample time of block (like using temp-fifo/RAM) but i can't figure it out and the fun thing is that doing something like that in VHDL is so easy
NB: a friend of mine has the same problem in Reed-Solomon code where from 188 byte-in he needs 204 byte-out! Please help us!!