hd-sdi interface testing

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paulr127

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Hi everyone
I need to test a design which has Xilinx SMPTE SDI Core which had HD-SDI interface..... It goes to rest of the components....

I am not conversant with it.

I have been asked to mimic that interface in my testbench and use the signals coming out of it as an input to test other components in the design.

I have not done that before. What does this mean and how do I mimic this interface and use it signals to test other components to the design to which it is connected to...

If anyone can tell me how do I do that please


Many thanks for your help
 

It means you're being asked to create an SDI signal over the interface as a behavioral model. This way you can test your blocks without using the Xilinx IP in the testbench.
I assume you know what the output of the Xilinx SDI core should look like?
 

I have not done that before. What does this mean and how do I mimic this interface and use it signals to test other components to the design to which it is connected to...
Click to expand...
You're essentially asked to build a BFM - Behavioral Functional Model.
Think of it as if you were given a task to design the far end side of the SDI...
But with one major waver - you're not constricted to writing purely synthesize code. This will allow you to use language contracts that are un-synthesizable but are functionally correct.
 
Thanks very much. Can anyone help me with its Behavioural Functional Model please? Many thanks
 

Sure.
There 3 important steps:
1. Read the SDI specification and understand how it works.
2. Write the code.
3. Test the code.
 

Thanks for your reply.

I would appreciate if you can point me to some reference bus functional model (if not particularly this) one so that I can get some idea of making those.

Many thanks
 

Honestly. Not completely and carefully as yet( Just a glance yet)
 

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