moretonslumber
Newbie level 1
Hello.
I have a design that must select from one of three source-synchronous clock/data sources. The clocks are unrelated and the selected one must be used directly to generate control signals for a bank of ADCs - I cannot shift the data to a fourth clock domain as the incoming clocks are from high tolerance sources. My problem is how do I implement and constrain a three way clock multiplexer? I'm experiencing different results each time I run P&R.
Any help greatly appreciated!
Graham.
I have a design that must select from one of three source-synchronous clock/data sources. The clocks are unrelated and the selected one must be used directly to generate control signals for a bank of ADCs - I cannot shift the data to a fourth clock domain as the incoming clocks are from high tolerance sources. My problem is how do I implement and constrain a three way clock multiplexer? I'm experiencing different results each time I run P&R.
Any help greatly appreciated!
Graham.