having PG ports (VDD and VSS) in Synthesis netlist is Good or Bad?

[krishnasasanka]

Hi All,
i am having PG ports (VDD and VSS) in my Synthesis netlist; i see having these in given RTL;
should i need to remove them or not.what happens if i forward to next steps using the same netlist?
how these PG ports effect the total flow if present in Synthesis netlist...
Please help me in understanding about this..

Thanks & Regards,
Sasanka

 

[rca]

During the RTL, the VDD/VSS ports is not necessary to be here. It will be added during the floorplan phase, when the power information is added.
Also when you used a UPF/CPF flow, the power ports are only added at the floorplan phase, instead there are known from a "functional" point of view via the UPF/CPF.

 

[RCircuit]

BE team might be not happy with PG ports in prelayout netlist.

 

[krishnasasanka]

Hi rca/RCircuit... Thanks a lot for the reply..
can you please explain what problems would be faced if the RTL has power ports?...

 

[rca]

If you add the port VDD & VSS for example, the synthesis tool will "used" them as usual signal.
Adding that during the floorplan, the ports and the nets will have the attribute "power", and not usual signal.
If the port are already here, I don't really know how the tool will accept / change the port attribute ...

 

[RCircuit]

How to add power ports in RTL? Or you add power ports in manually instantiated leaf gates in RTL?
I dont know if synthesis tool can add power ports in synthesized netlist which I have never tried.
Well, if your BE flow accepts power ports in prelayout netlist, then everything is ok.