sudhirkv
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I am using SI 3210 ProSLIC in my design and i dont have a perfect 1.024MHz clk, instead i derive a clock from my input 50MHZ clk of 1.0204 MHz and i am not able to access the ProSLIC. I saw the document of ProSLIC Initialization and i followed the steps as it is through a state machine. But still the SDO line of si 3210 is in high impedance. Pclk and FSync are in phase. i dont have any issues in having a seperate 1.024MHz clk in my design. Is there anything else i have to concentrate while accessing SPI of proslic.
Thanks in advance
Thanks in advance