has anybody simulated altera's ddr2 ip core?

[cgssuccess]

I use the quartus 12.1 to generate a ddr2 ip core;The fpga device is Cyclone IV;
I randomly selected a device preset and used its default parameters;then "generate simulation model " and "generate netlist" are selected!
But I found that there's a warning in the generation report;the picture is following;


The file "ddr2_ip_phy.v" is not generated,so i can't do the synthesis steps or the simulation steps;

I have tried to generate this ipcore in Quartus 11.0,12.1,13.0,but the same result is generated!

SO I need some supports!Thanks

 

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Maybe it's a problem specific to the Cyclone IV. I've done the same thing using 11.x on a Cyclone III and don't recall having that problem. Unfortunately I don't have the Quartus II installed so I can't check anything.