has a error when I schematic to verilog with cadence

[mpig09]

schematic to verilog

dear all:

i have a schematic that i want to transfer to verilog netlist, but i have a error
message, could anyone can help me?

ERROR :Cannot proceed with the explicit netlisging of the instance I26 in the view=
schematic, cell=Mux_8to1, lib=adc with hnlVerilogNetlistExplicit flag set. Either
there are spilt bus in the istance I26 or there is a bundle on the instance terminal.
You can continus netlisting by setting hnlVerilogNetlistExplicit to nil.

I have do these items:
1.transfer Mux_8to1: i can transfer this sch to a verilog netlist.
2.Set hnlVerilogNetlistExplicit = nil: undefine variable - hnlVerilogNetlistExplicit
so I can't use this setting.
mpig

 

[erikl]

cadence schematic to verilog

Either there are split bus in the instance I26 or there is a bundle on the instance terminal.

Probably the connection(s) to the instance terminal(s) are not correct.

 

[mpig09]

schematic to verilog cadence

I have checked the circuit, and the simulation result is right when I use hspice to simulate.

I have gaved up use cadence to create verilog model. I have wrote the code by myself.

mpig

 

[sdryk]

verilog cadence schematic

Old topic but I just got the problem and found a "solution"
I'm guessing your outputs (of the mux) are named out<1>, out<2>... as a bus type.

To solve it I had to rename all pinout out<1>, out<2>,... in out1, out2....
I have know idea why this is not supported anymore using spectreVerilog/ verilog.

May the solution be with you

sdryk