Hardware verification languages

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mkrtich.nazaryan

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Hi all,

I have a little time, and I'd like to learn a about HVL. But I'm new in this and need advice. I'm dealing with Verilog HDL (RTL level) and CMOS circuit design in transistor level. So which one is better?

1. OpenVera
2. e
3. SystemC
4.SystemVerilog

Thanks a lot.
 
Last edited:

Parev Mkrtich,

I have taken one class on SystemVerilog for verification. I know Verilog but am also a novice in verification as well. Try SystemVerilog because it has many constructs supported for both verification synthesis and it is object oriented. I can supply references if needed. SystemVerilog covers a great range of abstraction that can go even beyond the system level as in VHDL. I am not too familiar with the other languages so my response might be biased.

Vahe
 
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