Handoff Checks for Implementation

[deepika_11]

Hi All,

I need to build handoff checks for Implementation - So I need check for Libraries, netlist, SDC, UPF and DEF.

Checks should be the ones which impact Implementation and are not covered by people who are providing inputs -

i.e. - GCA and 0RC timing - for costraint checking will be executed by person handing over SDC

As an implmentation person, I need to write screener for PnR, capturing/covering anything/everything which will impact my QoR - at the same time making sure I am not repating checks being done by the experts (input providers)

Checks I have thought of are -
-> DEF and netlist consistency (because two different people are providng inputs, which might be clean but may not work togther)
-> Utilization report
-> congestion Map for better predictability - makes more sense if DCT is used for SYnthesis
-> check if all implementation corners are available in libraries
-> Data linking (DEF + netlist + UPF +SDC)
-> Leakage report of netlist - with summary of cells/ICGs/Vt types
-> Summary of clocks -> to check if clocks has required frequency
-> Clock domain crossing report -> to see if case analysis is ok
-> report_qor

Please suggest more checks, quick response is really appreciated. I want checks to be precise with their intent clear. Any checks worth capturing before PnR to ensure quality and completeness of input data is good.

 

[rca]

Could you indicate which step will be covered by your job?

 

[deepika_11]

Idea is to predict the quality of inputs and check the sanity/consistency of inputs before taking them to PnR flow. Hope that answers your question. Kind of screeing the inputs rather than starting Pnr and then finding issues later.

- - - Updated - - -

Idea is to predict the quality of inputs and check the sanity/consistency of inputs before taking them to PnR flow. Hope that answers your question. Kind of screeing the inputs rather than starting Pnr and then finding issues later. It is like early predictibility of possible issues and basic sanity checks mandatory for smooth run.

 

[rca]

you also need:
1- LEF files
2- power budget, to properly size the power ring.
3- pad/bump/bond placements
4- frontend-to-backend document which indicates:
a-some specific constraints/checks to add custom checks during backend flow.
b-list of net to buffer manually
c- ....
5- files for RC extractions
6- files for noise modeling
7- scan file order.
so far what I could think.

 

[deepika_11]

Thnaks but what I need is not the inputs, but the checks to be done on the inputs - assuming all inputs are in place

like if I get floorplan - I don't have to think about power budget/placement, it is already provided to me by the person doing the floorplan.
like if I get SDC, person should have done constraint checking with GCA and possibly 0 RC timing - anything else which oculd have been missed or makes sense for implementation - As i said synthesis frequency is pessimistic, so we might need to change the same for implementation.

I net list I can check - what is vt ratio to check for leakage, area distribution and congestion map - to have better awareness of my startpoint and if congestion map is too bad, I know i will get stuck. No assign statements , libarries completeness etc

Something on these lines -