# hand calculus and level49 model

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#### SwordFish

##### Member level 4 Hi,
How can I obtain parameters like KP, LAMBDA, GAMMA from a level 49 CMOS model.
I have a model for level 49 hspice for 0.18um. For hand calculus I need params like KP and LAMBDA. Can they be calculated from level 49. Or maybe because the level 49 is so complex the simulators don't use KP, LAMBDA or GAMMA. Can I approximate them with some empirical formula ??

bye

#### sutapanaki You're right - level49 is too complex to find KP etc. in it. Don't forget that Level1 models which you use for hand calculations were derived for long channel transistors (1u,2u..) where you don't have the short channel effects that you see in 0.18u and that level49 tries to model.
What I usually do, I make a simulation for the Id=f(Vgs) for some constant Vds and W/L and plot it. Then on the same plot I plot a function that describes the formula for hand calculating Id i.e.
(KP/2)(W/L)(Vgs-Vt)^2. Playing with KP (given Ialready know Vt) I can usually get a good fit of the two curves at least for Vgs up to about 1.2-1.5 volts. For higher Vgs the two curves diverge too much. This Kp is usually good for hand calculations in analog design. You have to repeat this for different W/L and different temperatures. From the collected data you can derive some average values. This is by no means accurate, the hand calculations give just a general ball-park figure. You will have to trim the circuit by simulations, but at least you start from a point that is closer to the truth. Usually the results are acceptable for saturation operation of transistors, but not good for triod operation.
As for LAMBDA - well, you have to find the Earli voltage. The problem is that if you extrapolate the Id-Vds curves untill they cross the abscisa, they don't meet at one point, which would be the Earli voltage. So, again you can get an impression about Lambda, but not very accurate one.
Another approach would be to ask your fab to give you these values, but usually they don't provide them if it is a digital CMOS process, because they don't care about them.
Hope it helps.

#### okguy

##### Full Member level 6 The appendice A1 of 'CMOS circuit design, layut and simulation' :
https://cmosedu.com/cmos1/book.htm
reply this issue. But, I cannot scan it for you. OkGuy.

#### superluminal

##### Member level 4 level 49 in Hspice is an enhanced version of BSIM3v3 model ( which is actually level 53 in Hspice & also in Eldo).

It is a very different model that contains many parameters concerning short channel effects & you can not get a resonable values for design with ( like KP , LAMBDA & GAMMA) . The only way , which is cool but not very effective , is what sutapanaki suggested- with some limitations ( remeber that short MOSFET has no square law dependence on Vgs , so the above method is good at small Vgs only).

The reason for no KP is that mobility is not constant & many factors enter to play in it ( physical & emperical).

No LAMBDA is defined , as in short MOSFET's there is many factors make Id not constant with Vd at constant Vgs. Not only the channel length modulation that affect the operation , there is many ( really too much !) factors also.

GAMMA is another mess ! many factors enter in body effect in BSIM (K1 , K2 ... ) & you find GAMMA1 & GAMMA2. GAMMA1 is the same as you use to do in hand calculation except that you use NCH ( channel doping ) for GAMMA1 instead of substrate doping (NSUB) in GAMMA2. So GAMMA1=sqrt(2*q*E*NCH / Cox') & GAMMA2=sqrt(2*q*E*NSUB / Cox') ( Cox' is another story !) . But using of K1 & K2 factors will discard the value of GAMMA1 & GAMMA2 , so it is effectively out of yard ( this if K1 & K2 is specified & this is the ordinary case as they are used to get Vth also).

You can try to use more "real" equations for this process [0.18] . I recommend you to see Rabaey (2nd edition , not first ! ) for cool simple ones. As I know , I can not find an analog design book that is embolden enough to write this equations AND let students design with it.

This can tell you how design ( & modeling as well) will be very challenging in the incoming years of 90nm & 65nm (SOI) generations !

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