This wall is the substrate, no conductor here except at the bottom of the wall, there is a bottom horizontal ground (which is a conductor).check this vertical thin wall is not conductor, ensure there are no any hidden walls inside substrate on this side:
I didn't define any boundaries or excitations to this wall. I tried to draw a vertical rectangle there and define it as "perfect H" and "symmetry perfect H" but the responses were almost the same.What is outer material on this wall? PML? or maybe HFSS puts PEC (conductor) by default?
Here are the S-parameters of the full-mode SIW (calculated at 50 ohms port impedance) using two different tapered widths.
when I simulated these two structures without the tapered microstrip feedlines, the cut-off frequency will be doubled!
From S-plot it is obvious that cutoff is around 5GHz, but it is not matched. Your Half-mode SIW S-plot shows big insertion loss around 5GHz. Probably placing waveguide port directly on HMSIW edge results in big mismatch, because port width is halved, but "magnetic wall" and symmetry does not act for port the same way as for waveguide. Solution would be to change something in port configuration, or to use transition as in your earlier post.
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