meghna
Junior Member level 3
Hi,
I am trying to search some papers on effect of half clock delay of comparator in sigma delta modulator. People model the effect of loop delay due to DAC pulse (say NRZ, RZ, HZ) but nobody tells that the comparator (quantizer or latch) in the loop will always give delay which should be taken into account always.
In other words, RZ pulse will be similar to HZ pulse when latch delay is included. It will cause some effect which can be compensated modifing the loop coefficient. But NRZ pulse will have its half clock shifted in next sampling phase which causes a third order term in loop gain (in case of second order modulator).
My question is 'how to model this term in s-domain'. In other words, I should be able to find this extra pole freqency in s domain.
Thanks & Regards
Meghna
I am trying to search some papers on effect of half clock delay of comparator in sigma delta modulator. People model the effect of loop delay due to DAC pulse (say NRZ, RZ, HZ) but nobody tells that the comparator (quantizer or latch) in the loop will always give delay which should be taken into account always.
In other words, RZ pulse will be similar to HZ pulse when latch delay is included. It will cause some effect which can be compensated modifing the loop coefficient. But NRZ pulse will have its half clock shifted in next sampling phase which causes a third order term in loop gain (in case of second order modulator).
My question is 'how to model this term in s-domain'. In other words, I should be able to find this extra pole freqency in s domain.
Thanks & Regards
Meghna
