Z
Zylen92
Guest
Hi fellow forum members,
In my digital design, the last module of the top module is a MUX. This MUX has 4 inputs which are 8 bit buses, 2 inputs which are selects and 1 output which is a 8 bit bus. When the synthesis is done(which is done without error), in the warning section I get this. Actually I never heed to the warning section but in this case, when I wrote a workbench and test the design, the output never changed .Although the individual input buses carried the signals to MUX without problem in testbench, after MUX there was no signal whatsoever, just UUUUUUUU.
Here is the warning;
Following is my MUX module,
In my digital design, the last module of the top module is a MUX. This MUX has 4 inputs which are 8 bit buses, 2 inputs which are selects and 1 output which is a 8 bit bus. When the synthesis is done(which is done without error), in the warning section I get this. Actually I never heed to the warning section but in this case, when I wrote a workbench and test the design, the output never changed .Although the individual input buses carried the signals to MUX without problem in testbench, after MUX there was no signal whatsoever, just UUUUUUUU.
Here is the warning;
Code:
WARNING:Pack:266 - The function generator
SawtoothModule/Mrom_dataout2_varindex00007 failed to merge with F5
multiplexer SawtoothModule/Mrom_dataout2_varindex00007_f6/MUXF5.I1. There is
a conflict for the GYMUX. The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator
SawtoothModule/Mrom_dataout2_varindex00007 failed to merge with F5
multiplexer TriangleModule/Mrom_dataout4_varindex00007_f6/MUXF5.I1. There is
a conflict for the GYMUX. The design will exhibit suboptimal timing.
Following is my MUX module,
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity MUXModule is Port( sinewave : in std_logic_vector ( 7 downto 0); sawtoothwave : in std_logic_vector ( 7 downto 0); squarewave : in std_logic_vector ( 7 downto 0); trianglewave : in std_logic_vector ( 7 downto 0); slct : in std_logic_vector (1 downto 0); amplitude : out std_logic_vector (7 downto 0)); end MUXModule; architecture Behavioral of MUXModule is begin process(slct,sawtoothwave, sinewave, squarewave, trianglewave) begin case slct is when "00" => amplitude <= sawtoothwave; when "01" => amplitude <= sinewave; when "10" => amplitude <= squarewave; when "11" => amplitude <= trianglewave; when others => amplitude <= "00000000"; end case; end process; end Behavioral;