By user :zhangjavier -"The PDK I am now using doesn't even provide me the model and layout of bondpad, so I have to design the bondpad layout myself and then extract the parasitics. The pad is to be used at about 3Ghz, so i want to know how to minimize the parasitical capacitance and resistance.And also i want it to be reliable."
Do I just connect all the metal layers with vias in the technology I am working with in Cadence virtuoso and run PEX simulation, which would give the model for bondpad?