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Guard rings in Cadence

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IC_layout_engineer

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I am practically new in using Cadence Virtuoso as a layout tool. I made a guard ring using Multipart Path. I wanted to know the layer composition of the guard ring. Can I flatten this auto-generated guard ring? Because aside from knowing the layers, I want to know how these layers were drawn.

I would appreciate any help. Thanks.

This is in connection with this thread:
https://www.edaboard.com/thread29922.html
 

bgangur

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Hi,

I would like to know what kind of GAURD RING you want to make in multi path like for PMOS or NMOS?
Layer composition depends upon the foundry.

Just defining the generic one
1. For PMOS device
Layer composition -- Diffusion + Nwell + Contact + Metal1
2. For NMOS device
Layer composition -- Diffusion + Pwell + Contact + Metal1

TSMC Example:
1. For PMOS device
Layer composition -- Diff (OD) + Nwell + NP (N Implant) + Contact + Metal1
2. For NMOS device
Layer composition -- Diff (OD) + Pwell + PP (P Implant) + Contact + Metal1

check proper overlap, width etc and construct.

Thanks and regards,
Basu
 

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