alecsander
Junior Member level 3
guard ring for silicon die
Hi!
I have a question about layouting the guard rings in CMOS technology. n+ or p+ guard rings are connected to power or ground.
Hastings of other books speaks only in general about these rings. But i have some small issues that i cannot find in books:
- how can i dimension the guard ring, not to be too thin, but also not to big?
- the metal of the guard ring must be cut? Some currents appear, and a current loop may form.
In general , can somebody help me with some advanced documentation on guard rings?
Thx,Alex.
Hi!
I have a question about layouting the guard rings in CMOS technology. n+ or p+ guard rings are connected to power or ground.
Hastings of other books speaks only in general about these rings. But i have some small issues that i cannot find in books:
- how can i dimension the guard ring, not to be too thin, but also not to big?
- the metal of the guard ring must be cut? Some currents appear, and a current loop may form.
In general , can somebody help me with some advanced documentation on guard rings?
Thx,Alex.